Publications and Presentations
From The Emerging Circuits and Computation Group at ITU
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Listed below are the papers, '''first authored''' by our group members as an indication that the related research is mainly conducted in our group, and the presentations. Research topics are ordered from newest to oldest as well as by considering their importance. Under each topic, papers are ordered from newest to oldest. All materials are subject to copyrights. | Listed below are the papers, '''first authored''' by our group members as an indication that the related research is mainly conducted in our group, and the presentations. Research topics are ordered from newest to oldest as well as by considering their importance. Under each topic, papers are ordered from newest to oldest. All materials are subject to copyrights. | ||
<div style="float:center; font-size:110%; font-weight:bold; clear:both; padding:0; margin:0.0em;">__TOC__</div> | <div style="float:center; font-size:110%; font-weight:bold; clear:both; padding:0; margin:0.0em;">__TOC__</div> | ||
− | == Computing with | + | |
+ | == Computing with Switching Lattices == | ||
=== Technology Development === | === Technology Development === | ||
+ | |||
+ | {| style="border:2px solid #abd5f5; background:#f1f5fc;" | ||
+ | | | ||
+ | {| | ||
+ | |- valign=top | ||
+ | | width="100" |'''title''': | ||
+ | | width="624"|[[Media:Akkan_EtAl_H_and_Square_Lattice_Technology_Development.pdf | Technology Development and Modeling of Switching Lattices Using Square and H Shaped Four-Terminal Switches]] | ||
+ | |- valign="top" | ||
+ | | '''authors''': | ||
+ | | width="550"| Nihat Akkan, Serzat Safaltin, Levent Aksoy, Ismail Cevik, Herman Sedef, Csaba Andras Moritz, and [[Mustafa Altun]] | ||
+ | |- valign="top" | ||
+ | | '''appeared in''': | ||
+ | | [http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=6245516 IEEE Transactions on Emerging Topics in Computing], early access, 2020. | ||
+ | |} | ||
+ | | align=center width="70" | | ||
+ | <span class="plainlinks"> | ||
+ | [[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/6/69/Akkan_EtAl_H_and_Square_Lattice_Technology_Development.pdf]]</span> | ||
+ | <br> | ||
+ | [[Media:Akkan_EtAl_H_and_Square_Lattice_Technology_Development.pdf | Paper]] | ||
+ | |} | ||
+ | |||
+ | {| style="border:2px solid #abd5f5; background:#f1f5fc;" | ||
+ | | | ||
+ | {| | ||
+ | |- valign=top | ||
+ | | width="100" |'''title''': | ||
+ | | width="550"|[[Media:Cevik_Aksoy_Altun_CMOS_Implementation_of_Switching_Lattices.pdf | CMOS Implementation of Switching Lattices]] | ||
+ | |- valign="top" | ||
+ | | '''authors''': | ||
+ | | Ismail Cevik, Levent Aksoy, and [[Mustafa Altun]] | ||
+ | |- valign="top" | ||
+ | | '''presented at''': | ||
+ | | [http://www.date-conference.com/ Design, Automation, and Test in Europe (DATE)], Grenoble, France, 2020. | ||
+ | |} | ||
+ | | align=center width="70" | | ||
+ | <span class="plainlinks"> | ||
+ | [[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/5/50/Cevik_Aksoy_Altun_CMOS_Implementation_of_Switching_Lattices.pdf]]</span> | ||
+ | <br> | ||
+ | [[Media:Cevik_Aksoy_Altun_CMOS_Implementation_of_Switching_Lattices.pdf | Paper]] | ||
+ | | align="center" width="70" | | ||
+ | <span class="plainlinks"> | ||
+ | |||
+ | [[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/1/1c/Cevik_Aksoy_Altun_CMOS_Implementation_of_Switching_Lattices.pptx]] | ||
+ | </span> | ||
+ | <br> [http://www.ecc.itu.edu.tr/images/1/1c/Cevik_Aksoy_Altun_CMOS_Implementation_of_Switching_Lattices.pptx Slides] | ||
+ | |} | ||
{| style="border:2px solid #abd5f5; background:#f1f5fc;" | {| style="border:2px solid #abd5f5; background:#f1f5fc;" | ||
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|} | |} | ||
− | === | + | === Logic Synthesis and Fault/Variation Tolerance === |
{| style="border:2px solid #abd5f5; background:#f1f5fc;" | {| style="border:2px solid #abd5f5; background:#f1f5fc;" | ||
Line 39: | Line 86: | ||
|- valign=top | |- valign=top | ||
| width="100" |'''title''': | | width="100" |'''title''': | ||
− | | width="550"|[[Media: | + | | width="550"|[[Media:Aksoy_Altun_Lattice_Synthesis_for_Complex_Functions.pdf | A Novel Method for the Realization of Complex Logic Functions Using Switching Lattices]] |
|- valign="top" | |- valign="top" | ||
| '''authors''': | | '''authors''': | ||
− | | | + | | Levent Aksoy and [[Mustafa Altun]] |
|- valign="top" | |- valign="top" | ||
| '''presented at''': | | '''presented at''': | ||
− | + | | [http://iscas2020.org/ IEEE International Symposium on Circuits and Systems (ISCAS)], Seville, Spain, 2020. | |
|} | |} | ||
| align=center width="70" | | | align=center width="70" | | ||
<span class="plainlinks"> | <span class="plainlinks"> | ||
− | [[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/ | + | [[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/7/72/Aksoy_Altun_Lattice_Synthesis_for_Complex_Functions.pdf]]</span> |
<br> | <br> | ||
− | [[Media: | + | [[Media:Aksoy_Altun_Lattice_Synthesis_for_Complex_Functions.pdf | Paper]] |
| align="center" width="70" | | | align="center" width="70" | | ||
<span class="plainlinks"> | <span class="plainlinks"> | ||
− | [[File: | + | [[File:MP4.jpg|60px|link=http://www.ecc.itu.edu.tr/images/7/7c/Aksoy_Altun_Lattice_Synthesis_for_Complex_Functions.mp4]] |
</span> | </span> | ||
− | <br> [http://www.ecc.itu.edu.tr/images/ | + | <br> [http://www.ecc.itu.edu.tr/images/7/7c/Aksoy_Altun_Lattice_Synthesis_for_Complex_Functions.mp4 Slides] |
+ | |} | ||
+ | |||
+ | {| style="border:2px solid #abd5f5; background:#f1f5fc;" | ||
+ | | | ||
+ | {| | ||
+ | |- valign=top | ||
+ | | width="100" |'''title''': | ||
+ | | width="624"|[[Media:Aksoy_Altun_Realizations_with_Switching_Lattices.pdf | Novel Methods for Efficient Realization of Logic Functions Using Switching Lattices]] | ||
+ | |- valign="top" | ||
+ | | '''authors''': | ||
+ | | Levent Aksoy and [[Mustafa Altun]] | ||
+ | |- valign="top" | ||
+ | | '''appeared in''': | ||
+ | | [http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12 IEEE Transactions on Computers], Vol. 69, Issue 3, pp. 427–440, 2020. | ||
+ | |} | ||
+ | | align=center width="70" | | ||
+ | <span class="plainlinks"> | ||
+ | [[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/e/e0/Aksoy_Altun_Realizations_with_Switching_Lattices.pdf]]</span> | ||
+ | <br> | ||
+ | [[Media:Aksoy_Altun_Realizations_with_Switching_Lattices.pdf | Paper]] | ||
|} | |} | ||
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|- valign=top | |- valign=top | ||
| width="100" |'''title''': | | width="100" |'''title''': | ||
− | | width="550"|[[Media: | + | | width="550"|[[Media: Aksoy_Altun_SAT_based_Synthesis_of_Switching_Lattices.pdf| A Satisfiability-Based Approximate Algorithm for Logic Synthesis Using Switching Lattices]] |
|- valign="top" | |- valign="top" | ||
| '''authors''': | | '''authors''': | ||
− | | | + | | Levent Aksoy and [[Mustafa Altun]] |
|- valign="top" | |- valign="top" | ||
| '''presented at''': | | '''presented at''': | ||
− | | width="550"| [http://www.date-conference.com/ Design, Automation and Test in Europe (DATE)], | + | | width="550"| [http://www.date-conference.com/ Design, Automation and Test in Europe (DATE)], Florence, Italy, 2019. |
|} | |} | ||
| align=center width="70" | | | align=center width="70" | | ||
<span class="plainlinks"> | <span class="plainlinks"> | ||
− | [[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/ | + | [[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/f/fe/Aksoy_Altun_SAT_based_Synthesis_of_Switching_Lattices.pdf]]</span> |
<br> | <br> | ||
− | [[Media: | + | [[Media:Aksoy_Altun_SAT_based_Synthesis_of_Switching_Lattices.pdf | Paper]] |
| align="center" width="70" | | | align="center" width="70" | | ||
<span class="plainlinks"> | <span class="plainlinks"> | ||
− | [[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/ | + | [[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/5/54/Aksoy_Altun_SAT_based_Synthesis_of_Switching_Lattices.pptx]] |
</span> | </span> | ||
− | <br> [http://www.ecc.itu.edu.tr/images/ | + | <br> [http://www.ecc.itu.edu.tr/images/5/54/Aksoy_Altun_SAT_based_Synthesis_of_Switching_Lattices.pptx Slides] |
|} | |} | ||
{| style="border:2px solid #abd5f5; background:#f1f5fc;" | {| style="border:2px solid #abd5f5; background:#f1f5fc;" | ||
− | |||
| | | | ||
{| | {| | ||
|- valign=top | |- valign=top | ||
| width="100" |'''title''': | | width="100" |'''title''': | ||
− | | width=" | + | | width="624"|[[Media:Morgul_Altun_Algorithms_for_Switching_Lattices.pdf | Optimal and Heuristic Algorithms to Synthesize Lattices of Four-Terminal Switches]] |
|- valign="top" | |- valign="top" | ||
| '''authors''': | | '''authors''': | ||
− | | | + | | Ceylan Morgul and [[Mustafa Altun]] |
− | |- valign=top | + | |- valign="top" |
| '''appeared in''': | | '''appeared in''': | ||
− | | width="624" | [http://www.journals.elsevier.com/ | + | | width="624" | [http://www.journals.elsevier.com/integration Integration, the VLSI Journal], Vol. 64, pp. 60–70, 2019. |
|} | |} | ||
| align=center width="70" | | | align=center width="70" | | ||
<span class="plainlinks"> | <span class="plainlinks"> | ||
− | [[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/ | + | [[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/5/58/Morgul_Altun_Algorithms_for_Switching_Lattices.pdf]]</span> |
<br> | <br> | ||
− | [[Media: | + | [[Media:Morgul_Altun_Algorithms_for_Switching_Lattices.pdf | Paper]] |
− | + | ||
|} | |} | ||
Line 114: | Line 179: | ||
|- valign=top | |- valign=top | ||
| width="100" |'''title''': | | width="100" |'''title''': | ||
− | | width=" | + | | width="624"|[[Media:Altun_Riedel_Logic_Synthesis_for_Switching_Lattices.pdf | Logic Synthesis for Switching Lattices]] |
|- valign="top" | |- valign="top" | ||
| '''authors''': | | '''authors''': | ||
− | | [[Mustafa Altun]] | + | | [[Mustafa Altun]] and Marc Riedel |
|- valign="top" | |- valign="top" | ||
+ | | '''appeared in''': | ||
+ | | [http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12 IEEE Transactions on Computers], Vol. 61, Issue 11, pp. 1588–1600, 2012. | ||
+ | <!-- |- valign="top" | ||
| '''presented at''': | | '''presented at''': | ||
− | | [http:// | + | | width="624"| [http://fias.uni-frankfurt.de International Conference on Computational Modelling of Nanostructured Materials (ICCMNM)-FIAS], Frankfurt, Germany, 2013. --> |
|} | |} | ||
| align=center width="70" | | | align=center width="70" | | ||
<span class="plainlinks"> | <span class="plainlinks"> | ||
− | [[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/ | + | [[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/c/ca/Altun_Riedel_Logic_Synthesis_for_Switching_Lattices.pdf]]</span> |
<br> | <br> | ||
− | [[Media: | + | [[Media:Altun_Riedel_Logic_Synthesis_for_Switching_Lattices.pdf | Paper]] |
− | + | ||
− | + | ||
− | + | ||
− | + | ||
− | + | ||
− | + | ||
|} | |} | ||
{| style="border:2px solid #abd5f5; background:#f1f5fc;" | {| style="border:2px solid #abd5f5; background:#f1f5fc;" | ||
− | |||
| | | | ||
{| | {| | ||
|- valign=top | |- valign=top | ||
| width="100" |'''title''': | | width="100" |'''title''': | ||
− | | width=" | + | | width="624"|[[Media:Altun_Riedel_Synthesizing_Logic_with_Percolation_in_Nanoscale_Lattices.pdf | Synthesizing Logic with Percolation in Nanoscale Lattices]] |
|- valign="top" | |- valign="top" | ||
| '''authors''': | | '''authors''': | ||
− | | | + | | [[Mustafa Altun]] and Marc Riedel |
+ | |- valign="top" | ||
+ | | '''appeared in''': | ||
+ | | [http://www.igi-global.com/Bookstore/TitleDetails.aspx?TitleId=1117&DetailsType=Description/ International Journal of Nanotechnology and Molecular Computation], Vol. 3, Issue 2, pp. 12–30, 2011. | ||
+ | |} | ||
+ | |||
+ | | align=center width="70" | | ||
+ | <span class="plainlinks"> | ||
+ | [[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/3/3b/Altun_Riedel_Synthesizing_Logic_with_Percolation_in_Nanoscale_Lattices.pdf]]</span> | ||
+ | <br> | ||
+ | [[Media:Altun_Riedel_Synthesizing_Logic_with_Percolation_in_Nanoscale_Lattices.pdf | Paper]] | ||
+ | |} | ||
+ | |||
+ | {| style="border:2px solid #abd5f5; background:#f1f5fc;" | ||
+ | | | ||
+ | {| | ||
|- valign=top | |- valign=top | ||
+ | | width="100" |'''title''': | ||
+ | | width="550"|[[Media:Altun_Riedel_Lattice-Based_Computation_of_Boolean_Functions.pdf | Lattice Based Computation of Boolean Functions]] | ||
+ | |- valign="top" | ||
+ | | '''authors''': | ||
+ | | [[Mustafa Altun]] and Marc Riedel | ||
+ | |- valign="top" | ||
| '''presented at''': | | '''presented at''': | ||
− | | [http:// | + | | [http://www.dac.com IEEE/ACM Design Automation Conference (DAC)], Anaheim, USA, 2010. |
|} | |} | ||
− | |||
| align=center width="70" | | | align=center width="70" | | ||
<span class="plainlinks"> | <span class="plainlinks"> | ||
− | [[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/ | + | [[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/7/7b/Altun_Riedel_Lattice-Based_Computation_of_Boolean_Functions.pdf]]</span> |
<br> | <br> | ||
− | [[Media: | + | [[Media:Altun_Riedel_Lattice-Based_Computation_of_Boolean_Functions.pdf | Paper]] |
| align="center" width="70" | | | align="center" width="70" | | ||
<span class="plainlinks"> | <span class="plainlinks"> | ||
− | [[File: | + | [[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/2/28/Altun_Riedel_Lattice-Based_Computation_of_Boolean_Functions.ppt]] |
</span> | </span> | ||
− | <br> [ | + | <br> [http://www.ecc.itu.edu.tr/images/2/28/Altun_Riedel_Lattice-Based_Computation_of_Boolean_Functions.ppt Slides] |
|} | |} | ||
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|- valign=top | |- valign=top | ||
| width="100" |'''title''': | | width="100" |'''title''': | ||
− | | width="550"|[[Media: | + | | width="550"|[[Media:Altun_Riedel_Neuhauser_Nanoscale_Digital_Computation_Through_Percolation.pdf | Nanoscale Digital Computation Through Percolation]] |
|- valign="top" | |- valign="top" | ||
| '''authors''': | | '''authors''': | ||
− | | | + | | [[Mustafa Altun]], Marc Riedel, and [http://www.cbs.umn.edu/eeb/contacts/claudia-neuhauser/ Claudia Neuhauser] |
|- valign=top | |- valign=top | ||
| '''presented at''': | | '''presented at''': | ||
− | | [http://www. | + | | [http://www.dac.com IEEE/ACM Design Automation Conference (DAC)], San Francisco, USA, 2009. |
|} | |} | ||
| align=center width="70" | | | align=center width="70" | | ||
<span class="plainlinks"> | <span class="plainlinks"> | ||
− | [[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/ | + | [[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/0/0c/Altun_Riedel_Neuhauser_Nanoscale_Digital_Computation_Through_Percolation.pdf]]</span> |
<br> | <br> | ||
− | [[Media: | + | [[Media:Altun_Riedel_Neuhauser_Nanoscale_Digital_Computation_Through_Percolation.pdf | Paper]] |
| align="center" width="70" | | | align="center" width="70" | | ||
<span class="plainlinks"> | <span class="plainlinks"> | ||
− | [[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/ | + | [[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/f/fe/Altun_Riedel_Neuhauser_Nanoscale_Digital_Computation_Through_Percolation.ppt]] |
</span> | </span> | ||
− | <br> [http://www.ecc.itu.edu.tr/images/ | + | <br> [http://www.ecc.itu.edu.tr/images/f/fe/Altun_Riedel_Neuhauser_Nanoscale_Digital_Computation_Through_Percolation.ppt Slides] |
|} | |} | ||
− | == | + | == Energy Efficient ANN Hardware Implementation == |
{| style="border:2px solid #abd5f5; background:#f1f5fc;" | {| style="border:2px solid #abd5f5; background:#f1f5fc;" | ||
Line 198: | Line 279: | ||
|- valign=top | |- valign=top | ||
| width="100" |'''title''': | | width="100" |'''title''': | ||
− | | width=" | + | | width="550"|[[Media:Aksoy_Parvin_Nojehdeh_Altun_Time_Multiplexed_ANN_Implementation.pdf | Efficient Time-Multiplexed Realization of Feedforward Artificial Neural Networks]] |
|- valign="top" | |- valign="top" | ||
| '''authors''': | | '''authors''': | ||
− | | | + | | Levent Aksoy, Sajjad Parvin, Mohammadreza Nojehdeh, and [[Mustafa Altun]] |
|- valign="top" | |- valign="top" | ||
− | | ''' | + | | '''presented at''': |
− | + | | [http://iscas2020.org/ IEEE International Symposium on Circuits and Systems (ISCAS)], Seville, Spain, 2020. | |
|} | |} | ||
| align=center width="70" | | | align=center width="70" | | ||
<span class="plainlinks"> | <span class="plainlinks"> | ||
− | [[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/ | + | [[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/e/eb/Aksoy_Parvin_Nojehdeh_Altun_Time_Multiplexed_ANN_Implementation.pdf]]</span> |
<br> | <br> | ||
− | [[Media: | + | [[Media:Aksoy_Parvin_Nojehdeh_Altun_Time_Multiplexed_ANN_Implementation.pdf | Paper]] |
+ | | align="center" width="70" | | ||
+ | <span class="plainlinks"> | ||
+ | |||
+ | [[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/3/3a/Aksoy_Parvin_Nojehdeh_Altun_Time_Multiplexed_ANN_Implementation.pptx]] | ||
+ | </span> | ||
+ | <br> [http://www.ecc.itu.edu.tr/images/3/3a/Aksoy_Parvin_Nojehdeh_Altun_Time_Multiplexed_ANN_Implementation.pptx Slides] | ||
|} | |} | ||
+ | |||
+ | == Computing with Nano-Crossbar Arrays == | ||
+ | |||
+ | === Comprehensive Performance Optimization=== | ||
{| style="border:2px solid #abd5f5; background:#f1f5fc;" | {| style="border:2px solid #abd5f5; background:#f1f5fc;" | ||
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|- valign=top | |- valign=top | ||
| width="100" |'''title''': | | width="100" |'''title''': | ||
− | | width=" | + | | width="550"|[[Media:Altun_EtAl_NANOxCOMP_Lessons_Learned_Future_Directions.pdf | Nano-Crossbar based Computing: Lessons Learned and Future Directions]] |
|- valign="top" | |- valign="top" | ||
| '''authors''': | | '''authors''': | ||
− | | | + | | [[Mustafa Altun]], Ismail Cevik, Ahmet Erten, Osman Eksik, Mircea Stan, and Csaba Andras Moritz |
|- valign="top" | |- valign="top" | ||
− | | ''' | + | | '''presented at''': |
− | + | | [http://www.date-conference.com/ Design, Automation, and Test in Europe (DATE)], Grenoble, France, 2020. | |
|} | |} | ||
| align=center width="70" | | | align=center width="70" | | ||
<span class="plainlinks"> | <span class="plainlinks"> | ||
− | [[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/ | + | [[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/0/04/Altun_EtAl_NANOxCOMP_Lessons_Learned_Future_Directions.pdf]]</span> |
<br> | <br> | ||
− | [[Media: | + | [[Media:Altun_EtAl_NANOxCOMP_Lessons_Learned_Future_Directions.pdf | Paper]] |
+ | | align="center" width="70" | | ||
+ | <span class="plainlinks"> | ||
+ | |||
+ | [[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/9/9f/Altun_EtAl_NANOxCOMP_Lessons_Learned_Future_Directions.pptx]] | ||
+ | </span> | ||
+ | <br> [http://www.ecc.itu.edu.tr/images/9/9f/Altun_EtAl_NANOxCOMP_Lessons_Learned_Future_Directions.pptx Slides] | ||
|} | |} | ||
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|- valign=top | |- valign=top | ||
| width="100" |'''title''': | | width="100" |'''title''': | ||
− | | width=" | + | | width="550"|[[Media: Morgul_EtAl_Integrated_Synthesis_Methodology for_Crossbar_Arrays.pdf | Integrated Synthesis Methodology for Crossbar Arrays]] |
|- valign="top" | |- valign="top" | ||
| '''authors''': | | '''authors''': | ||
− | | | + | | width="550"| Ceylan Morgul, Luca Frontini, Onur Tunali, Ioana Vatajelu, Valentina Ciriani, Lorena Anghel, Csaba Moritz, Mircea Stan, Dan Alexandrescu, and [[Mustafa Altun]] |
|- valign="top" | |- valign="top" | ||
− | | ''' | + | | '''presented at''': |
− | | width=" | + | | width="550"|[http://www.nanoarch.org/ IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH)], Athens, Greece, 2018. |
|} | |} | ||
| align=center width="70" | | | align=center width="70" | | ||
<span class="plainlinks"> | <span class="plainlinks"> | ||
− | [[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/ | + | [[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/b/b1/Morgul_EtAl_Integrated_Synthesis_Methodology_for_Crossbar_Arrays.pdf]]</span> |
<br> | <br> | ||
− | [[Media: | + | [[Media:Morgul_EtAl_Integrated_Synthesis_Methodology for_Crossbar_Arrays.pdf | Paper]] |
+ | | align="center" width="70" | | ||
+ | <span class="plainlinks"> | ||
+ | |||
+ | [[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/b/bd/Morgul_EtAl_Integrated_Synthesis_Methodology_for_Crossbar_Arrays.pptx]] | ||
+ | </span> | ||
+ | <br> [http://www.ecc.itu.edu.tr/images/b/bd/Morgul_EtAl_Integrated_Synthesis_Methodology_for_Crossbar_Arrays.pptx Slides] | ||
|} | |} | ||
Line 259: | Line 362: | ||
|- valign=top | |- valign=top | ||
| width="100" |'''title''': | | width="100" |'''title''': | ||
− | | width="550"|[[Media: | + | | width="550"|[[Media:Tunali_Altun_Logic_Synthesis_and_Defect_Tolerance_for_Memristive_Crossbars.pdf| Logic Synthesis and Defect Tolerance for Memristive Crossbar Arrays]] |
|- valign="top" | |- valign="top" | ||
| '''authors''': | | '''authors''': | ||
Line 265: | Line 368: | ||
|- valign="top" | |- valign="top" | ||
| '''presented at''': | | '''presented at''': | ||
− | | width="550"| [http:// | + | | width="550"| [http://www.date-conference.com/ Design, Automation and Test in Europe (DATE)], Dresden, Germany, 2018. |
|} | |} | ||
| align=center width="70" | | | align=center width="70" | | ||
<span class="plainlinks"> | <span class="plainlinks"> | ||
− | [[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/ | + | [[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/5/57/Tunali_Altun_Logic_Synthesis_and_Defect_Tolerance_for_Memristive_Crossbars.pdf]]</span> |
<br> | <br> | ||
− | [[Media: | + | [[Media:Tunali_Altun_Logic_Synthesis_and_Defect_Tolerance_for_Memristive_Crossbars.pdf | Paper]] |
| align="center" width="70" | | | align="center" width="70" | | ||
<span class="plainlinks"> | <span class="plainlinks"> | ||
− | [[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/ | + | [[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/b/b8/Tunali_Altun_Logic_Synthesis_and_Defect_Tolerance_for_Memristive_Crossbars.pptx]] |
</span> | </span> | ||
− | <br> [http://www.ecc.itu.edu.tr/images/ | + | <br> [http://www.ecc.itu.edu.tr/images/b/b8/Tunali_Altun_Logic_Synthesis_and_Defect_Tolerance_for_Memristive_Crossbars.pptx Slides] |
|} | |} | ||
{| style="border:2px solid #abd5f5; background:#f1f5fc;" | {| style="border:2px solid #abd5f5; background:#f1f5fc;" | ||
+ | |||
| | | | ||
{| | {| | ||
|- valign=top | |- valign=top | ||
| width="100" |'''title''': | | width="100" |'''title''': | ||
− | | width=" | + | | width="550"|[[Media:Altun_EtAl_Synthesis_and_Testing_for_Switching_Nano_Crossbar_Arrays.pdf | Logic Synthesis and Testing Techniques for Switching Nano-Crossbar Arrays]] |
|- valign="top" | |- valign="top" | ||
| '''authors''': | | '''authors''': | ||
− | | | + | | width="550"| Dan Alexandrescu, [[Mustafa Altun]], Lorena Anghel, Anna Bernasconi, Valentina Ciriani, Luca Frontini, and Mehdi Tahoori |
− | |- valign= | + | |- valign=top |
| '''appeared in''': | | '''appeared in''': | ||
− | | width="624" | [http:// | + | | width="624" | [http://www.journals.elsevier.com/microprocessors-and-microsystems/ Microprocessors and Microsystems], Vol. 54, pp. 14–25, 2017. |
|} | |} | ||
| align=center width="70" | | | align=center width="70" | | ||
<span class="plainlinks"> | <span class="plainlinks"> | ||
− | [[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/ | + | [[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/0/0a/Altun_EtAl_Synthesis_and_Testing_for_Switching_Nano_Crossbar_Arrays.pdf]]</span> |
<br> | <br> | ||
− | [[Media: | + | [[Media:Altun_EtAl_Synthesis_and_Testing_for_Switching_Nano_Crossbar_Arrays.pdf | Paper]] |
+ | |||
|} | |} | ||
Line 305: | Line 410: | ||
|- valign=top | |- valign=top | ||
| width="100" |'''title''': | | width="100" |'''title''': | ||
− | | width=" | + | | width="550"|[[Media:Altun_Ciriani_Tahoori_Computing_with_Nano-Crossbar_Arrays.pdf | Computing with Nano-Crossbar Arrays: Logic Synthesis and Fault Tolerance]] |
|- valign="top" | |- valign="top" | ||
| '''authors''': | | '''authors''': | ||
− | | | + | | [[Mustafa Altun]], Valentina Ciriani, and Mehdi Tahoori |
|- valign="top" | |- valign="top" | ||
− | | ''' | + | | '''presented at''': |
− | + | | [http://www.date-conference.com/ Design, Automation and Test in Europe (DATE)], Lausanne, Switzerland, 2017. | |
|} | |} | ||
| align=center width="70" | | | align=center width="70" | | ||
<span class="plainlinks"> | <span class="plainlinks"> | ||
− | [[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/ | + | [[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/0/09/Altun_Ciriani_Tahoori_Computing_with_Nano-Crossbar_Arrays.pdf]]</span> |
<br> | <br> | ||
− | [[Media: | + | [[Media:Altun_Ciriani_Tahoori_Computing_with_Nano-Crossbar_Arrays.pdf | Paper]] |
+ | | align="center" width="70" | | ||
+ | <span class="plainlinks"> | ||
+ | |||
+ | [[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/2/28/Altun_Ciriani_Tahoori_Computing_with_Nano-Crossbar_Arrays.pptx]] | ||
+ | </span> | ||
+ | <br> [http://www.ecc.itu.edu.tr/images/2/28/Altun_Ciriani_Tahoori_Computing_with_Nano-Crossbar_Arrays.pptx Slides] | ||
|} | |} | ||
{| style="border:2px solid #abd5f5; background:#f1f5fc;" | {| style="border:2px solid #abd5f5; background:#f1f5fc;" | ||
+ | |||
| | | | ||
{| | {| | ||
|- valign=top | |- valign=top | ||
| width="100" |'''title''': | | width="100" |'''title''': | ||
− | | width="550"|[[Media: | + | | width="550"|[[Media:Altun_EtAl_Synthesis_and_Performance_Optimization_of_a_Switching_Nano-crossbar_Computer.pdf | Synthesis and Performance Optimization of a Switching Nano-crossbar Computer]] |
|- valign="top" | |- valign="top" | ||
| '''authors''': | | '''authors''': | ||
− | | | + | | width="550"| Dan Alexandrescu, [[Mustafa Altun]], Lorena Anghel, Anna Bernasconi, Valentina Ciriani, and Mehdi Tahoori |
− | |- valign= | + | |- valign=top |
| '''presented at''': | | '''presented at''': | ||
− | + | | [http://dsd-seaa2016.cs.ucy.ac.cy/index.php Euromicro Conference on Digital System Design (DSD)], Limassol, Cyprus, 2016. | |
|} | |} | ||
+ | |||
| align=center width="70" | | | align=center width="70" | | ||
<span class="plainlinks"> | <span class="plainlinks"> | ||
− | [[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/ | + | [[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/a/ab/Altun_EtAl_Synthesis_and_Performance_Optimization_of_a_Switching_Nano-crossbar_Computer.pdf]]</span> |
<br> | <br> | ||
− | [[Media: | + | [[Media:Altun_EtAl_Synthesis_and_Performance_Optimization_of_a_Switching_Nano-crossbar_Computer.pdf | Paper]] |
| align="center" width="70" | | | align="center" width="70" | | ||
<span class="plainlinks"> | <span class="plainlinks"> | ||
− | [[File: | + | [[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/7/7f/Altun_EtAl_Synthesis_and_Performance_Optimization_of_a_Switching_Nano-crossbar_Computer_SLIDES.pdf]] |
</span> | </span> | ||
− | <br> [ | + | <br> [[Media:Altun_EtAl_Synthesis_and_Performance_Optimization_of_a_Switching_Nano-crossbar_Computer_SLIDES.pdf | Slides]] |
|} | |} | ||
{| style="border:2px solid #abd5f5; background:#f1f5fc;" | {| style="border:2px solid #abd5f5; background:#f1f5fc;" | ||
+ | |||
| | | | ||
{| | {| | ||
|- valign=top | |- valign=top | ||
| width="100" |'''title''': | | width="100" |'''title''': | ||
− | | width=" | + | | width="550"|[[Media:Morgul_Peker_Altun_Power-Delay-Area_Performance_Modeling_and_Analysis_for_Nano-Crossbar_Arrays.pdf | Power-Delay-Area Performance Modeling and Analysis for Nano-Crossbar Arrays]] |
|- valign="top" | |- valign="top" | ||
| '''authors''': | | '''authors''': | ||
− | | [[Mustafa Altun]] | + | | Ceylan Morgul, Furkan Peker, and [[Mustafa Altun]] |
− | |- valign= | + | |- valign=top |
− | | ''' | + | | '''presented at''': |
− | | [http://www. | + | | [http://www.eng.ucy.ac.cy/theocharides/isvlsi16/ IEEE Computer Society Annual Symposium on VLSI (ISVLSI)], Pittsburgh, USA, 2016. |
|} | |} | ||
| align=center width="70" | | | align=center width="70" | | ||
<span class="plainlinks"> | <span class="plainlinks"> | ||
− | [[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/ | + | [[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/8/8f/Morgul_Peker_Altun_Power-Delay-Area_Performance_Modeling_and_Analysis_for_Nano-Crossbar_Arrays.pdf]]</span> |
<br> | <br> | ||
− | [[Media: | + | [[Media:Morgul_Peker_Altun_Power-Delay-Area_Performance_Modeling_and_Analysis_for_Nano-Crossbar_Arrays.pdf | Paper]] |
+ | | align="center" width="70" | | ||
+ | <span class="plainlinks"> | ||
+ | |||
+ | [[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/5/5a/Morgul_Peker_Altun_Power-Delay-Area_Performance_Modeling_and_Analysis_for_Nano-Crossbar_Arrays.pptx]] | ||
+ | </span> | ||
+ | <br> [http://www.ecc.itu.edu.tr/images/5/5a/Morgul_Peker_Altun_Power-Delay-Area_Performance_Modeling_and_Analysis_for_Nano-Crossbar_Arrays.pptx Poster] | ||
|} | |} | ||
− | + | === Logic Synthesis and Fault/Variation Tolerance === | |
+ | {| style="border:2px solid #abd5f5; background:#f1f5fc;" | ||
| | | | ||
{| | {| | ||
|- valign=top | |- valign=top | ||
| width="100" |'''title''': | | width="100" |'''title''': | ||
− | | width=" | + | | width="624"|[[Media:Tunali_Altun_Multiple_type_Defect_Tolerance_in_Nano_Crossbar_Arrays.pdf | A Fast Logic Mapping Algorithm for Multiple-type-Defect Tolerance in Reconfigurable Nano-Crossbar Arrays]] |
|- valign="top" | |- valign="top" | ||
| '''authors''': | | '''authors''': | ||
− | | [[Mustafa Altun] | + | | Onur Tunali and [[Mustafa Altun]] |
− | |- valign=top | + | |- valign="top" |
− | | ''' | + | | '''appeared in''': |
− | | [http:// | + | | width="624" | [http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=6245516 IEEE Transactions on Emerging Topics in Computing], Vol. 7, Issue 4, pp. 518–529, 2019. |
|} | |} | ||
− | |||
| align=center width="70" | | | align=center width="70" | | ||
<span class="plainlinks"> | <span class="plainlinks"> | ||
− | [[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/ | + | [[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/c/c9/Tunali_Altun_Multiple_type_Defect_Tolerance_in_Nano_Crossbar_Arrays.pdf]]</span> |
<br> | <br> | ||
− | [[Media: | + | [[Media:Tunali_Altun_Multiple_type_Defect_Tolerance_in_Nano_Crossbar_Arrays.pdf | Paper]] |
− | + | ||
− | + | ||
− | + | ||
− | + | ||
− | + | ||
− | + | ||
|} | |} | ||
− | |||
− | |||
{| style="border:2px solid #abd5f5; background:#f1f5fc;" | {| style="border:2px solid #abd5f5; background:#f1f5fc;" | ||
Line 402: | Line 514: | ||
|- valign=top | |- valign=top | ||
| width="100" |'''title''': | | width="100" |'''title''': | ||
− | | width=" | + | | width="624"|[[Media:Tunali_Morgul_Altun_Defect_Tolerant_Memristor_Crossbars.pdf | Defect Tolerant Logic Synthesis for Memristor Crossbars with Performance Evaluation]] |
|- valign="top" | |- valign="top" | ||
| '''authors''': | | '''authors''': | ||
− | | | + | | Onur Tunali, Ceylan Morgul, and [[Mustafa Altun]] |
|- valign="top" | |- valign="top" | ||
− | | ''' | + | | '''appeared in''': |
− | | [http:// | + | | width="624" | [http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=40 IEEE Micro], Vol. 38, Issue 5, pp. 22–31, 2018. |
|} | |} | ||
| align=center width="70" | | | align=center width="70" | | ||
<span class="plainlinks"> | <span class="plainlinks"> | ||
− | [[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/ | + | [[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/d/db/Tunali_Morgul_Altun_Defect_Tolerant_Memristor_Crossbars.pdf]]</span> |
<br> | <br> | ||
− | [[Media: | + | [[Media:Tunali_Morgul_Altun_Defect_Tolerant_Memristor_Crossbars.pdf | Paper]] |
− | + | ||
− | + | ||
− | + | ||
− | + | ||
− | + | ||
− | + | ||
|} | |} | ||
Line 428: | Line 534: | ||
|- valign=top | |- valign=top | ||
| width="100" |'''title''': | | width="100" |'''title''': | ||
− | | width="624"|[[Media: | + | | width="624"|[[Media:Peker_Altun_Variation_Tolerant_Logic_Mapping_of_Nano_Crossbars.pdf | A Fast Hill Climbing Algorithm for Defect and Variation Tolerant Logic Mapping of Nano-Crossbar Arrays]] |
|- valign="top" | |- valign="top" | ||
| '''authors''': | | '''authors''': | ||
− | | | + | | Furkan Peker and [[Mustafa Altun]] |
|- valign="top" | |- valign="top" | ||
− | | ''' | + | | '''appeared in''': |
− | | [http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber= | + | | width="624" | [http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=6687315 IEEE Transactions on Multi-Scale Computing Systems], Vol. 4, No. 4, pp. 522–532, 2018. |
|} | |} | ||
| align=center width="70" | | | align=center width="70" | | ||
<span class="plainlinks"> | <span class="plainlinks"> | ||
− | [[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/ | + | [[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/7/71/Peker_Altun_Variation_Tolerant_Logic_Mapping_of_Nano_Crossbars.pdf]]</span> |
<br> | <br> | ||
− | [[Media: | + | [[Media:Peker_Altun_Variation_Tolerant_Logic_Mapping_of_Nano_Crossbars.pdf | Paper]] |
|} | |} | ||
Line 449: | Line 555: | ||
|- valign=top | |- valign=top | ||
| width="100" |'''title''': | | width="100" |'''title''': | ||
− | | width="550"|[[Media: | + | | width="550"|[[Media:Tunali_Altun_Nano_Crossbar_Yield_Analysis.pdf| Yield Analysis of Nano-Crossbar Arrays for Uniform and Clustered Defect Distributions]] |
|- valign="top" | |- valign="top" | ||
| '''authors''': | | '''authors''': | ||
− | | | + | | Onur Tunali and [[Mustafa Altun]] |
|- valign="top" | |- valign="top" | ||
| '''presented at''': | | '''presented at''': | ||
− | | width="550"| [http:// | + | | width="550"| [http://icecs2017.org/ IEEE International Conference on Electronics Circuits and Systems (ICECS)], Batumi, Georgia, 2017. |
|} | |} | ||
| align=center width="70" | | | align=center width="70" | | ||
<span class="plainlinks"> | <span class="plainlinks"> | ||
− | [[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/ | + | [[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/6/6b/Tunali_Altun_Nano_Crossbar_Yield_Analysis.pdf]]</span> |
<br> | <br> | ||
− | [[Media: | + | [[Media:Tunali_Altun_Nano_Crossbar_Yield_Analysis.pdf | Paper]] |
| align="center" width="70" | | | align="center" width="70" | | ||
<span class="plainlinks"> | <span class="plainlinks"> | ||
− | [[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/ | + | [[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/6/62/Tunali_Altun_Nano_Crossbar_Yield_Analysis.pptx]] |
</span> | </span> | ||
− | <br> [http://www.ecc.itu.edu.tr/images/ | + | <br> [http://www.ecc.itu.edu.tr/images/6/62/Tunali_Altun_Nano_Crossbar_Yield_Analysis.pptx Slides] |
|} | |} | ||
Line 475: | Line 581: | ||
|- valign=top | |- valign=top | ||
| width="100" |'''title''': | | width="100" |'''title''': | ||
− | | width="624"|[[Media: | + | | width="624"|[[Media:Tunali_Altun_A_Survey_of_Nano-crossbar_Fault_Tolerance.pdf | A Survey of Fault Tolerance Algorithms for Reconfigurable Nano-Crossbar Arrays]] |
|- valign="top" | |- valign="top" | ||
| '''authors''': | | '''authors''': | ||
− | | | + | | Onur Tunali and [[Mustafa Altun]] |
|- valign="top" | |- valign="top" | ||
| '''appeared in''': | | '''appeared in''': | ||
− | | width="624" | [http:// | + | | width="624" | [http://csur.acm.org/ ACM Computing Surveys], Vol. 50, No. 6, Article 79, 2017. |
|} | |} | ||
| align=center width="70" | | | align=center width="70" | | ||
<span class="plainlinks"> | <span class="plainlinks"> | ||
− | [[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/ | + | [[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/b/bc/Tunali_Altun_A_Survey_of_Nano-crossbar_Fault_Tolerance.pdf]]</span> |
<br> | <br> | ||
− | [[Media: | + | [[Media:Tunali_Altun_A_Survey_of_Nano-crossbar_Fault_Tolerance.pdf | Paper]] |
|} | |} | ||
{| style="border:2px solid #abd5f5; background:#f1f5fc;" | {| style="border:2px solid #abd5f5; background:#f1f5fc;" | ||
− | |||
| | | | ||
{| | {| | ||
|- valign=top | |- valign=top | ||
| width="100" |'''title''': | | width="100" |'''title''': | ||
− | | width=" | + | | width="624"|[[Media:Tunali_Altun_Permanent_and_Transient_Fault_Tolerance_for_Reconfigurable_Nano-Crossbar_Arrays.pdf | Permanent and Transient Fault Tolerance for Reconfigurable Nano-Crossbar Arrays]] |
|- valign="top" | |- valign="top" | ||
| '''authors''': | | '''authors''': | ||
− | | | + | | Onur Tunali and [[Mustafa Altun]] |
− | |- valign=top | + | |- valign="top" |
− | | ''' | + | | '''appeared in''': |
− | | width=" | + | | width="624" | [http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=43 IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems], Vol. 36, Issue 5, pp. 747–760, 2017. |
|} | |} | ||
− | |||
| align=center width="70" | | | align=center width="70" | | ||
<span class="plainlinks"> | <span class="plainlinks"> | ||
− | [[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/ | + | [[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/c/cc/Tunali_Altun_Permanent_and_Transient_Fault_Tolerance_for_Reconfigurable_Nano-Crossbar_Arrays.pdf]]</span> |
<br> | <br> | ||
− | [[Media: | + | [[Media:Tunali_Altun_Permanent_and_Transient_Fault_Tolerance_for_Reconfigurable_Nano-Crossbar_Arrays.pdf | Paper]] |
− | + | ||
− | + | ||
− | + | ||
− | + | ||
− | + | ||
− | + | ||
|} | |} | ||
Line 523: | Line 621: | ||
|- valign=top | |- valign=top | ||
| width="100" |'''title''': | | width="100" |'''title''': | ||
− | | width=" | + | | width="550"|[[Media:Tunali_Altun_Defect_Tolerance_in_Diode_FET_and_Four-Terminal_Switch_based_Nano-Crossbar_Arrays.pdf | Defect Tolerance in Diode FET and Four-Terminal Switch Based Nano-Crossbar Arrays]] |
|- valign="top" | |- valign="top" | ||
| '''authors''': | | '''authors''': | ||
− | | [[Mustafa Altun]] | + | | Onur Tunali and [[Mustafa Altun]] |
|- valign="top" | |- valign="top" | ||
− | |||
− | |||
− | |||
| '''presented at''': | | '''presented at''': | ||
− | | width=" | + | | width="550"|[http://www.nanoarch.org/ IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH)], Boston, USA, 2015. |
|} | |} | ||
| align=center width="70" | | | align=center width="70" | | ||
<span class="plainlinks"> | <span class="plainlinks"> | ||
− | [[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/ | + | [[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/e/ee/Tunali_Altun_Defect_Tolerance_in_Diode_FET_and_Four-Terminal_Switch_based_Nano-Crossbar_Arrays.pdf]]</span> |
<br> | <br> | ||
− | [[Media: | + | [[Media:Tunali_Altun_Defect_Tolerance_in_Diode_FET_and_Four-Terminal_Switch_based_Nano-Crossbar_Arrays.pdf | Paper]] |
+ | | align="center" width="70" | | ||
+ | <span class="plainlinks"> | ||
+ | |||
+ | [[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/f/f9/Tunali_Altun_Defect_Tolerance_in_Diode_FET_and_Four-Terminal_Switch_based_Nano-Crossbar_Arrays.pptx]] | ||
+ | </span> | ||
+ | <br> [http://www.ecc.itu.edu.tr/images/f/f9/Tunali_Altun_Defect_Tolerance_in_Diode_FET_and_Four-Terminal_Switch_based_Nano-Crossbar_Arrays.pptx Slides] | ||
|} | |} | ||
{| style="border:2px solid #abd5f5; background:#f1f5fc;" | {| style="border:2px solid #abd5f5; background:#f1f5fc;" | ||
+ | |||
| | | | ||
{| | {| | ||
|- valign=top | |- valign=top | ||
| width="100" |'''title''': | | width="100" |'''title''': | ||
− | | width="550"|[[Media: | + | | width="550"|[[Media:Morgul_Altun_Synthesis_and_Optimization_of_Switching_Nanoarrays.pdf | Synthesis and Optimization of Switching Nanoarrays]] |
|- valign="top" | |- valign="top" | ||
| '''authors''': | | '''authors''': | ||
− | | [[Mustafa Altun]] | + | | Ceylan Morgul and [[Mustafa Altun]] |
− | |- valign= | + | |- valign=top |
| '''presented at''': | | '''presented at''': | ||
− | | [http://www. | + | | width="550"| [http://www.ddecs2015.org/ IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS)], Belgrade, Serbia, 2015. |
|} | |} | ||
+ | |||
| align=center width="70" | | | align=center width="70" | | ||
<span class="plainlinks"> | <span class="plainlinks"> | ||
− | [[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/ | + | [[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/5/59/Morgul_Altun_Synthesis_and_Optimization_of_Switching_Nanoarrays.pdf]]</span> |
<br> | <br> | ||
− | [[Media: | + | [[Media:Morgul_Altun_Synthesis_and_Optimization_of_Switching_Nanoarrays.pdf | Paper]] |
| align="center" width="70" | | | align="center" width="70" | | ||
<span class="plainlinks"> | <span class="plainlinks"> | ||
− | [[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/ | + | [[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/1/1a/Morgul_Altun_Synthesis_and_Optimization_of_Switching_Nanoarrays.pptx]] |
</span> | </span> | ||
− | <br> [http://www.ecc.itu.edu.tr/images/ | + | <br> [http://www.ecc.itu.edu.tr/images/1/1a/Morgul_Altun_Synthesis_and_Optimization_of_Switching_Nanoarrays.pptx Slides] |
|} | |} | ||
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</span> | </span> | ||
<br> [http://www.ecc.itu.edu.tr/images/a/aa/Morgul_Altun_Anahtarlamali_Nano_Dizinler_ile_Lojik_Devre_Tasarimi_ve_Boyut_Optimizasyonu.pptx Slides] | <br> [http://www.ecc.itu.edu.tr/images/a/aa/Morgul_Altun_Anahtarlamali_Nano_Dizinler_ile_Lojik_Devre_Tasarimi_ve_Boyut_Optimizasyonu.pptx Slides] | ||
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|- valign=top | |- valign=top | ||
| '''presented at''': | | '''presented at''': | ||
− | | [http://www. | + | | [http://www.eng.ucy.ac.cy/theocharides/isvlsi16/ IEEE Computer Society Annual Symposium on VLSI (ISVLSI)], Pittsburgh, USA, 2016. |
|} | |} | ||
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== Approximate Computing == | == Approximate Computing == | ||
+ | |||
+ | {| style="border:2px solid #abd5f5; background:#f1f5fc;" | ||
+ | | | ||
+ | {| | ||
+ | |- valign=top | ||
+ | | width="100" |'''title''': | ||
+ | | width="550"|[[Media:Nojehdeh_Aksoy_Altun_Approximate_ANN.pdf | Efficient Hardware Implementation of Artificial Neural Networks Using Approximate Multiply-Accumulate Blocks]] | ||
+ | |- valign="top" | ||
+ | | '''authors''': | ||
+ | | Mohammadreza Nojehdeh, Levent Aksoy, and [[Mustafa Altun]] | ||
+ | |- valign=top | ||
+ | | '''presented at''': | ||
+ | | [http://www.eng.ucy.ac.cy/theocharides/isvlsi20/ IEEE Computer Society Annual Symposium on VLSI (ISVLSI)], Limassol, Cyprus, 2020. | ||
+ | |} | ||
+ | |||
+ | | align=center width="70" | | ||
+ | <span class="plainlinks"> | ||
+ | [[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/b/bd/Nojehdeh_Aksoy_Altun_Approximate_ANN.pdf]]</span> | ||
+ | <br> | ||
+ | [[Media:Nojehdeh_Aksoy_Altun_Approximate_ANN.pdf | Paper]] | ||
+ | | align="center" width="70" | | ||
+ | <span class="plainlinks"> | ||
+ | |||
+ | [[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/7/7f/Nojehdeh_Aksoy_Altun_Approximate_ANN.pptx]] | ||
+ | </span> | ||
+ | <br> [http://www.ecc.itu.edu.tr/images/7/7f/Nojehdeh_Aksoy_Altun_Approximate_ANN.pptx Slides] | ||
+ | |} | ||
{| style="border:2px solid #abd5f5; background:#f1f5fc;" | {| style="border:2px solid #abd5f5; background:#f1f5fc;" | ||
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|- valign=top | |- valign=top | ||
| '''presented at''': | | '''presented at''': | ||
− | | [http://www. | + | | [http://www.eng.ucy.ac.cy/theocharides/isvlsi17/ IEEE Computer Society Annual Symposium on VLSI (ISVLSI)], Bochum, Germany, 2017. |
|} | |} | ||
Revision as of 17:29, 19 October 2020
Listed below are the papers, first authored by our group members as an indication that the related research is mainly conducted in our group, and the presentations. Research topics are ordered from newest to oldest as well as by considering their importance. Under each topic, papers are ordered from newest to oldest. All materials are subject to copyrights.
Computing with Switching Lattices
Technology Development
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Logic Synthesis and Fault/Variation Tolerance
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Energy Efficient ANN Hardware Implementation
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Computing with Nano-Crossbar Arrays
Comprehensive Performance Optimization
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Logic Synthesis and Fault/Variation Tolerance
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National Publications in Turkish
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Stochastic and Bit Stream Computing
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National Publications in Turkish
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Approximate Computing
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National Publications in Turkish
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Large-Area Electronics
Transistor Fabrication
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Organic Transistor Modeling
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Reversible Computing
CMOS Fault Tolerance
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Logic Synthesis
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National Publications in Turkish
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Reliability of Electronic Products
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National Publications in Turkish
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Analog Circuit Design
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National Publications in Turkish
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Discrete Mathematics
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