Publications and Presentations
From The Emerging Circuits and Computation Group at ITU
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=== Fault/Defect/Variation Tolerance === | === Fault/Defect/Variation Tolerance === | ||
+ | |||
+ | {| style="border:2px solid #abd5f5; background:#f1f5fc;" | ||
+ | | | ||
+ | {| | ||
+ | |- valign=top | ||
+ | | width="100" |'''title''': | ||
+ | | width="624"|[[Media:Tunali_Altun_Multiple_type_Defect_Tolerance_in_Nano_Crossbar_Arrays.pdf | A Fast Logic Mapping Algorithm for Multiple-type-Defect Tolerance in Reconfigurable Nano-Crossbar Arrays]] | ||
+ | |- valign="top" | ||
+ | | '''authors''': | ||
+ | | Onur Tunali and [[Mustafa Altun]] | ||
+ | |- valign="top" | ||
+ | | '''appeared in''': | ||
+ | | width="624" | [http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=6245516 IEEE Transactions on Emerging Topics in Computing], Vol. 7, Issue 4, pp. 518–529 2019. | ||
+ | |} | ||
+ | | align=center width="70" | | ||
+ | <span class="plainlinks"> | ||
+ | [[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/c/c9/Tunali_Altun_Multiple_type_Defect_Tolerance_in_Nano_Crossbar_Arrays.pdf]]</span> | ||
+ | <br> | ||
+ | [[Media:Tunali_Altun_Multiple_type_Defect_Tolerance_in_Nano_Crossbar_Arrays.pdf | Paper]] | ||
+ | |} | ||
{| style="border:2px solid #abd5f5; background:#f1f5fc;" | {| style="border:2px solid #abd5f5; background:#f1f5fc;" | ||
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</span> | </span> | ||
<br> [http://www.ecc.itu.edu.tr/images/6/62/Tunali_Altun_Nano_Crossbar_Yield_Analysis.pptx Slides] | <br> [http://www.ecc.itu.edu.tr/images/6/62/Tunali_Altun_Nano_Crossbar_Yield_Analysis.pptx Slides] | ||
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|} | |} | ||
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=== Logic Synthesis === | === Logic Synthesis === | ||
+ | |||
+ | {| style="border:2px solid #abd5f5; background:#f1f5fc;" | ||
+ | | | ||
+ | {| | ||
+ | |- valign=top | ||
+ | | width="100" |'''title''': | ||
+ | | width="624"|[[Media:Aksoy_Altun_Realizations_with_Switching_Lattices.pdf | Novel Methods for Efficient Realization of Logic Functions Using Switching Lattices]] | ||
+ | |- valign="top" | ||
+ | | '''authors''': | ||
+ | | Levent Aksoy and [[Mustafa Altun]] | ||
+ | |- valign="top" | ||
+ | | '''accepted in''': | ||
+ | | [http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12 IEEE Transactions on Computers], 2019. | ||
+ | |} | ||
+ | | align=center width="70" | | ||
+ | <span class="plainlinks"> | ||
+ | [[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/e/e0/Aksoy_Altun_Realizations_with_Switching_Lattices.pdf]]</span> | ||
+ | <br> | ||
+ | [[Media:Aksoy_Altun_Realizations_with_Switching_Lattices.pdf | Paper]] | ||
+ | |} | ||
{| style="border:2px solid #abd5f5; background:#f1f5fc;" | {| style="border:2px solid #abd5f5; background:#f1f5fc;" | ||
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|- valign="top" | |- valign="top" | ||
| '''appeared in''': | | '''appeared in''': | ||
− | | [http:// | + | | [http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12 IEEE Transactions on Computers], Vol. 61, Issue 11, pp. 1588–1600, 2012. |
<!-- |- valign="top" | <!-- |- valign="top" | ||
| '''presented at''': | | '''presented at''': | ||
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|} | |} | ||
− | == Reversible | + | == Reversible Computing == |
+ | |||
+ | === CMOS Fault Tolerance === | ||
+ | |||
+ | {| style="border:2px solid #abd5f5; background:#f1f5fc; " | ||
+ | |||
+ | | | ||
+ | {| | ||
+ | |- valign=top | ||
+ | | width="100" |'''title''': | ||
+ | | width="624"|[[Media:Parvin_Altun_Perfect_Concurrent_Fault_Detection.pdf| Perfect Concurrent Fault Detection in CMOS Logic Circuits Using Parity Preservative Reversible Gates | ||
+ | ]] | ||
+ | |- valign="top" | ||
+ | | '''authors''': | ||
+ | | Sajjad Parvin and [[Mustafa Altun]] | ||
+ | |- valign="top" | ||
+ | | '''appeared in''': | ||
+ | | [http://ieeeaccess.ieee.org/ IEEE Access], Vol. 7, pp. 163939–163947, 2019. | ||
+ | |} | ||
+ | | align=center width="70" | | ||
+ | <span class="plainlinks"> | ||
+ | [[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/3/3c/Parvin_Altun_Perfect_Concurrent_Fault_Detection.pdf]]</span> | ||
+ | <br> | ||
+ | [[Media:Parvin_Altun_Perfect_Concurrent_Fault_Detection.pdf | Paper]] | ||
+ | |||
+ | |} | ||
+ | |||
+ | {| style="border:2px solid #abd5f5; background:#f1f5fc;" | ||
+ | |||
+ | | | ||
+ | {| | ||
+ | |- valign=top | ||
+ | | width="100" |'''title''': | ||
+ | | width="550"|[[Media:Parvin_Altun_CMOS_Fault_Tolerance_with_Preservative_Reversible_Gates.pdf | Implementation of CMOS Logic Circuits with Perfect Fault Detection Using Preservative Reversible Gates]] | ||
+ | |- valign="top" | ||
+ | | '''authors''': | ||
+ | | Sajjad Parvin and [[Mustafa Altun]] | ||
+ | |- valign=top | ||
+ | | '''presented at''': | ||
+ | | width="550"| [http://tima.univ-grenoble-alpes.fr/conferences/iolts/iolts19/ IEEE International Symposium on On-Line Testing and Robust System Design (IOLTS)], Rhodes Island, Greece, 2019. | ||
+ | |} | ||
+ | |||
+ | | align=center width="70" | | ||
+ | <span class="plainlinks"> | ||
+ | [[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/e/ee/Parvin_Altun_CMOS_Fault_Tolerance_with_Preservative_Reversible_Gates.pdf]]</span> | ||
+ | <br> | ||
+ | [[Media:Parvin_Altun_CMOS_Fault_Tolerance_with_Preservative_Reversible_Gates.pdf | Paper]] | ||
+ | | align="center" width="70" | | ||
+ | <span class="plainlinks"> | ||
+ | |||
+ | [[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/f/f4/Parvin_Altun_CMOS_Fault_Tolerance_with_Preservative_Reversible_Gates.pptx]] | ||
+ | </span> | ||
+ | <br> [http://www.ecc.itu.edu.tr/images/f/f4/Parvin_Altun_CMOS_Fault_Tolerance_with_Preservative_Reversible_Gates.pptx Poster] | ||
+ | |} | ||
{| style="border:2px solid #abd5f5; background:#f1f5fc; " | {| style="border:2px solid #abd5f5; background:#f1f5fc; " | ||
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|} | |} | ||
+ | |||
+ | === Logic Synthesis === | ||
{| style="border:2px solid #abd5f5; background:#f1f5fc; " | {| style="border:2px solid #abd5f5; background:#f1f5fc; " | ||
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== Approximate Computing == | == Approximate Computing == | ||
+ | |||
+ | {| style="border:2px solid #abd5f5; background:#f1f5fc;" | ||
+ | | | ||
+ | {| | ||
+ | |- valign=top | ||
+ | | width="100" |'''title''': | ||
+ | | width="624"|[[Media:Nojehdeh_Altun_Approximate_Adders_Multipliers.pdf | Systematic Synthesis of Approximate Adders and Multipliers with Accurate Error Calculations]] | ||
+ | |- valign="top" | ||
+ | | '''authors''': | ||
+ | | Mohammadreza Nojehdeh and [[Mustafa Altun]] | ||
+ | |- valign="top" | ||
+ | | '''appeared in''': | ||
+ | | width="624" | [http://www.journals.elsevier.com/integration Integration, the VLSI Journal], Vol. 70, pp. 99–107, 2020. | ||
+ | |} | ||
+ | | align=center width="70" | | ||
+ | <span class="plainlinks"> | ||
+ | [[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/c/c8/Nojehdeh_Altun_Approximate_Adders_Multipliers.pdf]]</span> | ||
+ | <br> | ||
+ | [[Media:Nojehdeh_Altun_Approximate_Adders_Multipliers.pdf | Paper]] | ||
+ | |} | ||
{| style="border:2px solid #abd5f5; background:#f1f5fc; " | {| style="border:2px solid #abd5f5; background:#f1f5fc; " | ||
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== Large-Area Electronics == | == Large-Area Electronics == | ||
+ | |||
+ | === Transistor Fabrication === | ||
+ | |||
+ | {| style="border:2px solid #abd5f5; background:#f1f5fc;" | ||
+ | |||
+ | | | ||
+ | {| | ||
+ | |- valign=top | ||
+ | | width="100" |'''title''': | ||
+ | | width="550"|[[Media:Yedikardes_EtAl_P3HT_WO3_Organic_Transistors.pdf | The Enhanced Electronic Properties of P3HT-WO3 Hybrid Thin Film Transistors]] | ||
+ | |- valign="top" | ||
+ | | '''authors''': | ||
+ | | width="550"|Beyza Yedikardes, Fereshteh Ordokhani, Nihat Akkan, Ece Kurt, Esra Zayim, Nilgün Yavuz, and [[Mustafa Altun]] | ||
+ | |- valign=top | ||
+ | | '''presented at''': | ||
+ | | width="550"| [http://www.advanced-nanomaterials-conference.com/ International Conference on Advanced Nanomaterials (ANM)], Aveiro, Portugal, 2019. | ||
+ | |} | ||
+ | |||
+ | | align=center width="70" | | ||
+ | <span class="plainlinks"> | ||
+ | [[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/d/d5/Yedikardes_EtAl_P3HT_WO3_Organic_Transistors.pdf]]</span> | ||
+ | <br> | ||
+ | [[Media:Yedikardes_EtAl_P3HT_WO3_Organic_Transistors.pdf | Abstract]] | ||
+ | | align="center" width="70" | | ||
+ | <span class="plainlinks"> | ||
+ | |||
+ | [[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/2/25/Yedikardes_EtAl_P3HT_WO3_Organic_Transistors.pptx]] | ||
+ | </span> | ||
+ | <br> [http://www.ecc.itu.edu.tr/images/2/25/Yedikardes_EtAl_P3HT_WO3_Organic_Transistors.pptx Slides] | ||
+ | |} | ||
=== Organic Transistor Modeling === | === Organic Transistor Modeling === |
Revision as of 16:30, 5 December 2019
Listed below are the papers, first authored by our group members as an indication that the related research is mainly conducted in our group, and the presentations. Research topics are ordered from newest to oldest as well as by considering their importance. Under each topic, papers are ordered from newest to oldest. All materials are subject to copyrights.
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Computing with Nano-Crossbar Arrays
Technology Development
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Comprehensive Performance Optimization
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Fault/Defect/Variation Tolerance
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Logic Synthesis
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National Publications in Turkish
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Reversible Computing
CMOS Fault Tolerance
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Logic Synthesis
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National Publications in Turkish
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Stochastic and Bit Stream Computing
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National Publications in Turkish
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Approximate Computing
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National Publications in Turkish
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Large-Area Electronics
Transistor Fabrication
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Organic Transistor Modeling
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Reliability of Electronic Products
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National Publications in Turkish
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Analog Circuit Design
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National Publications in Turkish
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Discrete Mathematics
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