Research

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<h2 style="margin:.1em; border-bottom:1px; font-size:140%; font-weight:bold;"> Computing with Switching Lattices </h2>
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|-
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| valign="top" style="padding:8px 8px 0px 8px; background:#f5fffa;" <!--H210 S4 V100--> |
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A switching lattice, formed as a two dimensional network of four-terminal switches, is introduced as a crossbar based, regular, dense, area-efficient, and CMOS-compatible structure for logic computing. A four-terminal switch, corresponding to a crossbar cross-point or a lattice site, has one control input and four terminals. The control input makes all of its terminals either all disconnected (OFF) or all connected (ON).
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[[Image:research_lattice_logic.png|center|none|800px|link=]]
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<h3>
 +
Technology Development</h3>
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 +
We show that '''switching lattices are CMOS-compatible'''. For this purpose, we propose
 +
different four-terminal switch structures, and construct them in three dimensional
 +
technology computer-aided design (TCAD) environment as well as in Cadence environment satisfying the design rules of the TSMC 65nm CMOS process and perform
 +
simulations.
 +
Experimental results show that the realization of logic functions using switching lattices occupy '''much less layout area''' and have
 +
competitive delay and power consumption values when compared to the conventional CMOS implementations.
 +
 
 +
[[Image:research_lattice_technology.png|center|none|800px|link=]]
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<h3>
 +
Performance Optimization</h3>
 +
We propose a logic synthesis algorithm to optimize '''lattice sizes under a delay constraint'''. We also propose '''static and dynamic logic solutions for area-delay-power efficiency''' of the lattices.
 +
<!-- [[Image:Research-2.png|center|none|800px|link=]] -->
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<h3>
 +
Synthesis</h3>
 +
We propose '''optimal and heuristic''' algorithms to implement logic functions with minimum size switching lattices.
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<!-- [[Image:Research-1.png|center|none|800px|link=]] -->
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|- valign=top
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| width="696" |'''Selected Publications'''
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|}
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|
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{|
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|- valign=top
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| width="100" |'''title''':
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| width="450"|[[Media: Akkan_EtAl_H_and_Square_Lattice_Technology_Development.pdf | Technology Development and Modeling of Switching Lattices Using Square and H Shaped Four-Terminal Switches]]
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|- valign="top"
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| '''authors''':
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| width="450"| Nihat Akkan, Serzat Safaltin, Levent Aksoy, Ismail Cevik, Herman Sedef, Csaba Andras Moritz, and [[Mustafa Altun]]
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|- valign="top"
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| '''appeared&nbsp;in''':
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| width="450" | [http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=6245516 IEEE Transactions on Emerging Topics in Computing], early access, 2020.
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|- valign=top
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| '''presented&nbsp;at''':
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| width="450"| [http://www.date-conference.com/ Design, Automation and Test in Europe (DATE)], Grenoble, France, 2020.
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|}
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| align=center width="70" |
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<span class="plainlinks">
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[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/6/69/Akkan_EtAl_H_and_Square_Lattice_Technology_Development.pdf]]</span>
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<br>
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[[Media:Akkan_EtAl_H_and_Square_Lattice_Technology_Development.pdf | Paper]]
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| align="center" width="70" |
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<span class="plainlinks">
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[[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/1/1c/Cevik_Aksoy_Altun_CMOS_Implementation_of_Switching_Lattices.pptx]]
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</span>
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<br> [http://www.ecc.itu.edu.tr/images/1/1c/Cevik_Aksoy_Altun_CMOS_Implementation_of_Switching_Lattices.pptx Slides]
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|}
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{| style="border:1px solid #abd5f5; background:#f1f5fc;"
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|
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{|
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|- valign=top
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| width="100" |'''title''':
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| width="450"|[[Media:Aksoy_Altun_Realizations_with_Switching_Lattices.pdf | Novel Methods for Efficient Realization of Logic Functions Using Switching Lattices]]
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|- valign="top"
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| '''authors''':
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| Levent Aksoy and [[Mustafa Altun]]
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|- valign="top"
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| '''appeared&nbsp;in''':
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| width="450" | [http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12 IEEE Transactions on Computers], Vol. 69, Issue 3, pp. 427&ndash;440, 2020.
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|- valign="top"
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| '''presented&nbsp;at''':
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| width="450"| [http://www.date-conference.com/ Design, Automation and Test in Europe (DATE)], Florence, Italy, 2019.
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|}
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| align=center width="70" |
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<span class="plainlinks">
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[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/e/e0/Aksoy_Altun_Realizations_with_Switching_Lattices.pdf]]</span>
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<br>
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[[Media:Aksoy_Altun_Realizations_with_Switching_Lattices.pdf | Paper]]
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| align="center" width="70" |
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<span class="plainlinks">
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[[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/5/54/Aksoy_Altun_SAT_based_Synthesis_of_Switching_Lattices.pptx]]
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</span>
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<br> [http://www.ecc.itu.edu.tr/images/5/54/Aksoy_Altun_SAT_based_Synthesis_of_Switching_Lattices.pptx Slides]
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|- valign=top
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| width="696" |'''Funding Projects'''
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|
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{|
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|- valign="top"
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| width="140" |'''title''':
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| width="558"| Implementation of 3D Nano Stuctures and Switching Lattices
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|- valign="top"
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| '''agency & program''':
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| width="450"| [https://ufuk2020.org.tr/en/content/tubitak-nsf-joint-research-program TUBITAK-NSF Joint Research Program (2501)]
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|- valign="top"
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| '''budget''':
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| 720.000 TL
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|- valign="top"
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| '''duration''':
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| 2019-2022
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|}
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{| style="margin-left: auto; margin-right: 0px; border:0.1px solid #abd5ff; background:#f1f5fc; padding:0.2em 0em;"
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|- valign="top"
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| width="140" |'''project goal''':
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| width="558"| Design, fabrication, and test of switching lattices and nano-crossbars within 3D interconnect architectures.
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|}
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|}
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|-
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<h2 style="margin:.1em; border-bottom:1px; font-size:140%; font-weight:bold;"> Energy Efficient ANN Hardware Implementation </h2>
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|-
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| valign="top" style="padding:8px 8px 0px 8px; background:#f5fffa;" <!--H210 S4 V100--> |
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We aim to use '''hardware aware training''' techniques, new '''hybrid bit parallel-serial''' number representations, and constant multiplication based '''sharing''' techniques to reduce energy consumption of feed-forward artificial neural networks (ANNs).
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[[Image:research_ANN.png|center|none|800px|link=]]
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|- valign=top
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| width="696" |'''Selected Publications'''
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|}
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{| style="border:1px solid #abd5f5; background:#f1f5fc;"
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|
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{|
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|- valign=top
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| width="100" |'''title''':
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| width="450"| [[Media:Aksoy_Parvin_Nojehdeh_Altun_Time_Multiplexed_ANN_Implementation.pdf | Efficient Time-Multiplexed Realization of Feedforward Artificial Neural Networks]]
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|- valign="top"
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| '''authors''':
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| Levent Aksoy, Sajjad Parvin, Mohammadreza Nojehdeh, and [[Mustafa Altun]]
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|- valign="top"
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| '''presented&nbsp;at''':
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| width="450"| [http://iscas2020.org/ IEEE International Symposium on Circuits and Systems (ISCAS)], Seville, Spain, 2020.
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|}
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| align=center width="70" |
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<span class="plainlinks">
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[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/e/eb/Aksoy_Parvin_Nojehdeh_Altun_Time_Multiplexed_ANN_Implementation.pdf]]</span>
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<br>
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[[Media:Aksoy_Parvin_Nojehdeh_Altun_Time_Multiplexed_ANN_Implementation.pdf | Paper]]
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| align="center" width="70" |
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<span class="plainlinks">
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[[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/3/3a/Aksoy_Parvin_Nojehdeh_Altun_Time_Multiplexed_ANN_Implementation.pptx]]
 +
</span>
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<br> [http://www.ecc.itu.edu.tr/images/3/3a/Aksoy_Parvin_Nojehdeh_Altun_Time_Multiplexed_ANN_Implementation.pptx Slides]
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|- valign=top
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| width="696" |'''Funding Projects'''
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|}
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{| style="margin-left: auto; margin-right: 0px; border:1px solid #abd5f5; background:#f1f5fc;"
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|
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{|
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|- valign="top"
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| width="140" |'''title''':
 +
| width="558"|Energy-Efficient Hardware Design of Artificial Neural Networks (ANNs) for Mobile Platforms
 +
|- valign="top"
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| '''agency & program''':
 +
| [http://www.tubitak.gov.tr/tr/destekler/akademik/ulusal-destek-programlari/icerik-1001-bilimsel-ve-teknolojik-arastirma-projelerini-destekleme-pr TUBITAK Scientific and Technological Research Projects Funding Program (1001)]
 +
|- valign="top"
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| '''budget''':
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| 400.000 TL
 +
|- valign="top"
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| '''duration''':
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| 2020-2023
 +
|}
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{| style="margin-left: auto; margin-right: 0px; border:0.1px solid #abd5ff; background:#f1f5fc; padding:0.2em 0em;"
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|- valign="top"
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| width="140" |'''project goal''':
 +
| width="558"| Implementing energy-efficient ANNs by changing the rules of computing from the level of number representations to the level of circuit and system design.
 +
 
 +
|}
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|}
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{|
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|- valign=top
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| width="140" |'''title''':
 +
| width="558"| Gate and Transistor Implementations of Accurate Arithmetic Operation Blocks with Stochastic Logic
 +
|- valign="top"
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| '''agency & program''':
 +
| [http://bap.itu.edu.tr/ Istanbul Technical University Research Support Program (ITU-BAP)]
 +
|- valign="top"
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| '''duration''':
 +
| 2017-2019
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|}
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<h2 style="margin:.1em; border-bottom:1px; font-size:140%; font-weight:bold;"> Computing with Nano-Crossbar Arrays </h2>
 
<h2 style="margin:.1em; border-bottom:1px; font-size:140%; font-weight:bold;"> Computing with Nano-Crossbar Arrays </h2>
  
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Although a four-terminal switch based array offers a '''significant area advantage''', in terms of the number of switches, compared to the ones having two-terminal switches, its realization at the technology level needs
 
Although a four-terminal switch based array offers a '''significant area advantage''', in terms of the number of switches, compared to the ones having two-terminal switches, its realization at the technology level needs
 
further justifications and raises a number of questions about its
 
further justifications and raises a number of questions about its
feasibility. We answer these questions. First, by using
+
feasibility. We answer these questions. By using
 
three dimensional technology computer-aided design (TCAD)
 
three dimensional technology computer-aided design (TCAD)
simulations, we show that '''four-terminal switches can be directly implemented with the CMOS technology'''. For this purpose, we
+
simulations, we show that '''four-terminal switches can be directly implemented with the CMOS technology'''. Then, by fitting the TCAD simulation data
try different semiconductor gate materials in different formations
+
of geometric shapes. Then, by fitting the TCAD simulation data
+
 
to the standard CMOS current-voltage equations, we develop a
 
to the standard CMOS current-voltage equations, we develop a
Spice model of a four-terminal switch. Finally, we successfully
+
Spice model of a four-terminal switch.  
perform '''Spice circuit simulations on four-terminal switches''' with
+
different sizes.
+
[[Image:research_lattice_technology.png|center|none|800px|link=]]
+
  
 
<h3>
 
<h3>
 
Performance Optimization</h3>
 
Performance Optimization</h3>
  
We study crossbar arrys including the memristive ones. We
+
We study crossbar arrays including the memristive ones. We
 
propose a '''defect-tolerant logic synthesis algorithms by considering area, delay, and power costs''' of the arrays.
 
propose a '''defect-tolerant logic synthesis algorithms by considering area, delay, and power costs''' of the arrays.
 
<!-- [[Image:Research-2.png|center|none|800px|link=]] -->
 
<!-- [[Image:Research-2.png|center|none|800px|link=]] -->
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| width="696" |'''Funding Projects'''
 
| width="696" |'''Funding Projects'''
 
|}
 
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{| style="margin-left: auto; margin-right: 0px; border:1px solid #abd5f5; background:#f1f5fc;"
 
 
|
 
{|
 
|- valign="top"
 
| width="140" |'''title''':
 
| width="558"| Computing with Switching Lattices: Technology Development, Device Modeling, and Circuit Design
 
|- valign="top"
 
| '''agency & program''':
 
| width="450"| [http://www.tubitak.gov.tr/en/content-2501-joint-research-program-with-national-science-foundation-nsf TUBITAK-NSF Joint Research Program (2501)]
 
|- valign="top"
 
| '''budget''':
 
| 720.000 TL
 
|- valign="top"
 
| '''duration''':
 
| 2019-2022
 
|}
 
{| style="margin-left: auto; margin-right: 0px; border:0.1px solid #abd5ff; background:#f1f5fc; padding:0.2em 0em;"
 
|- valign="top"
 
| width="140" |'''project goal''':
 
| width="558"| Developing a new CMOS-compatible technology based on switching lattice structures that consumes much less area compared to the conventional CMOS technology, and introducing an EDA methodology that designs digital circuits with switching lattices.
 
 
|}
 
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| '''duration''':
 
| '''duration''':
| 2015-2019
+
| 2015-2019, ''completed''
 
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<h2 style="margin:.1em; border-bottom:1px; font-size:140%; font-weight:bold;"> Reversible Computing </h2>
+
<h2 style="margin:.1em; border-bottom:1px; font-size:140%; font-weight:bold;"> Stochastic and Bit Stream Computing </h2>
 
|-
 
|-
 
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Unlike conventional CMOS circuits, reversible circuits do not have latent faults, so faults occurring in internal circuit nodes
+
We propose a novel computing paradigm “Bit Stream Computing (BSC)” that does not necessarily employ randomly or Binomially distributed bit streams as stochastic
always result in an error at the output. This is a unique feature for online or concurrent fault tolerance. Motivated by this, we implement error tolerant CMOS circuit blocks by exploiting reversible computing. We first synthesize reversible circuits with reversible gates; then we make them fault-tolerant; and  finally we perform conversion from reversible gates to CMOS gates.
+
computing does. '''Any type of streams can be used either stochastic
 +
or deterministic'''. The proposed paradigm benefits from the area
 +
advantage of stochastic logic and the accuracy advantage of
 +
conventional binary logic. We implement '''accurate arithmetic
 +
multiplier and adder circuits''', classified as asynchronous or
 +
synchronous. We believe that this study '''opens
 +
up new horizons for computing that enables us to implement
 +
much smaller yet accurate arithmetic circuits''' compared to the
 +
conventional binary and stochastic ones.
  
 +
<!-- <h3>
 +
Accurate Arithmetic Implementations</h3>
  
[[Image:Research-reversible-2.png|center|none|800px|link=]]
+
We propose a method to overcome the main drawback in stochastic computing, '''low accuracy''' or related '''long computing times'''. Our method manipulates stochastic bit streams with the aid of feedback mechanisms. We implement error-free arithmetic multiplier and adder circuits by considering performance parameters area, delay, and accuracy. -->
 +
[[Image:Research_Bit_Stream.png|center|none|800px|link=]]
  
<h3>
 
 
Perfect Online Error Detection </h3>
 
 
In order to achieve a CMOS circuit having '''100% online or concurrent error detection''', we exploit reversible computing by proposing a new, fault preservative, and reversible gate library. We ensure that the parity, even or odd, is preserved at all levels including the output level unless there is a faulty node.
 
<!--<h3>
 
 
Synthesis </h3>
 
 
We propose a fast synthesis algorithm that implements any given reversible Boolean function with reversible gates. Instead of an exhaustive search on every given function, our algorithm creates a library of '''essential functions''' and performs '''sorting'''. As an example, to implement 4 bit circuits we only use 120 essential functions out of all 20922789888000 functions. We also perform optimization for both '''reversible and quantum circuit costs''' by considering adjacent gate pairs.
 
-->
 
<h3>
 
 
Online Error Detection and Correction </h3>
 
 
We develop two techniques to make a reversible circuit fault-tolerant by using multiple-control Toffoli gates. The first technique is based on '''single parity preserving''', and offers error detection for odd number of errors at the output. The second technique is constructed on '''Hamming codes for error correction'''. We also claim that perfect error detection is possible with conservative reversible gates such as a Fredkin gate. As the next step, we '''utilize the proposed reversible circuits with conventional CMOS gates'''.
 
 
<!-- [[Image:Research-4.png|center|none|800px|link=]] -->
 
 
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| width="696" |'''Selected Publications'''
 
| width="696" |'''Selected Publications'''
 
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| width="100" |'''title''':
 
| width="100" |'''title''':
| width="450"|[[Media:Parvin_Altun_CMOS_Fault_Tolerance_with_Preservative_Reversible_Gates.pdf | Implementation of CMOS Logic Circuits with Perfect Fault Detection Using Preservative Reversible Gates]]
+
| width="450"|[[Media:Vahapoglu_Altun_From_Stochastic_To_Bit_Stream_Computing.pdf | From Stochastic to Bit Stream Computing: Accurate Implementation of Arithmetic Circuits and Applications in Neural Networks]]
 
|- valign="top"
 
|- valign="top"
 
| '''authors''':
 
| '''authors''':
| Sajjad Parvin and [[Mustafa Altun]]
+
| Ensar Vahapoglu and [[Mustafa Altun]]
|- valign=top
+
| '''presented&nbsp;at''':
+
| width="450"| [http://tima.univ-grenoble-alpes.fr/conferences/iolts/iolts19/ IEEE International Symposium on On-Line Testing and Robust System Design (IOLTS)], Rhodes Island, Greece, 2019.
+
|}
+
 
+
| align=center width="70" |
+
<span class="plainlinks">
+
[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/e/ee/Parvin_Altun_CMOS_Fault_Tolerance_with_Preservative_Reversible_Gates.pdf]]</span>
+
<br>
+
[[Media:Parvin_Altun_CMOS_Fault_Tolerance_with_Preservative_Reversible_Gates.pdf | Paper]]
+
| align="center" width="70" |
+
<span class="plainlinks">
+
 
+
[[File:PPT.jpg|60px|link=]]
+
</span>
+
<br> Poster
+
|}
+
 
+
{| style="border:1px solid #abd5f5; background:#f1f5fc;"
+
|
+
{|
+
|- valign=top
+
| width="100" |'''title''':
+
| width="524"|[[Media:Altun_Parvin_Cilasun_Exploiting_Reversible_Computing_for_CMOS_Fault_Tolerance.pdf| Exploiting Reversible Computing for Latent-Fault-Free Error Detecting/Correcting CMOS Circuits
+
]]
+
|- valign="top"
+
| '''authors''':
+
| [[Mustafa Altun]], Sajjad Parvin, and Husrev Cilasun
+
 
|- valign="top"
 
|- valign="top"
 
| '''appeared&nbsp;in''':
 
| '''appeared&nbsp;in''':
| [http://ieeeaccess.ieee.org/ IEEE Access], Vol. 6, pp. 74475&ndash;74484, 2018.
+
| arXiv, 1805.06262, 2018.
|}
+
| align=center width="70" |
+
<span class="plainlinks">
+
[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/7/7d/Altun_Parvin_Cilasun_Exploiting_Reversible_Computing_for_CMOS_Fault_Tolerance.pdf]]</span>
+
<br>
+
[[Media:Altun_Parvin_Cilasun_Exploiting_Reversible_Computing_for_CMOS_Fault_Tolerance.pdf | Paper]]
+
|}
+
 
+
<!-- {| style="border:1px solid #abd5f5; background:#f1f5fc;"
+
 
+
|
+
{|
+
 
|- valign=top
 
|- valign=top
| width="100" |'''title''':
 
| width="450"|[[Media:Susam_Altun_Fast_Synthesis_of_Reversible_Circuits_using_a_Sorting_Algorithm_and_Optimization.pdf| Fast Synthesis of Reversible Circuits using a Sorting Algorithm and Optimization]]
 
|- valign="top"
 
| '''authors''':
 
| Omercan Susam and [[Mustafa Altun]]
 
|- valign="top"
 
| '''appeared&nbsp;in''':
 
| width="450"| [http://www.oldcitypublishing.com/journals/mvlsc-home/ Journal of Multiple-Valued Logic and Soft Computing], Vol. 29, Issue 1-2, pp. 1&ndash;23, 2017.
 
|- valign="top"
 
 
| '''presented&nbsp;at''':
 
| '''presented&nbsp;at''':
| width="450"| [http://www.ieee-icecs2014.org/ IEEE International Conference on Electronics Circuits and Systems (ICECS)], Marseille, France, 2014.
+
| width="450"| [http://www.isvlsi.org/ IEEE Computer Society Annual Symposium on VLSI (ISVLSI)], Pittsburgh, USA, 2016.
 
|}
 
|}
 
| align=center width="70" |
 
| align=center width="70" |
 
<span class="plainlinks">
 
<span class="plainlinks">
[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/c/cd/Susam_Altun_Fast_Synthesis_of_Reversible_Circuits_using_a_Sorting_Algorithm_and_Optimization.pdf]]</span>
+
[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/7/73/Vahapoglu_Altun_From_Stochastic_To_Bit_Stream_Computing.pdf]]</span>
 
<br>
 
<br>
[[Media:Susam_Altun_Fast_Synthesis_of_Reversible_Circuits_using_a_Sorting_Algorithm_and_Optimization.pdf | Paper]]
+
[[Media:Vahapoglu_Altun_From_Stochastic_To_Bit_Stream_Computing.pdf | Paper]]
 
| align="center" width="70" |
 
| align="center" width="70" |
 
<span class="plainlinks">
 
<span class="plainlinks">
  
[[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/d/d0/Susam_Altun_An_Efficient_Algorithm_to_Synthesize_Quantum_Circuits_and_Optimization.pptx]]
+
[[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/d/d6/Vahapoglu_Altun_Accurate_Synthesis_of_Arithmetic_Operations_with_Stochastic_Logic.pptx]]
 
</span>
 
</span>
<br> [http://www.ecc.itu.edu.tr/images/d/d0/Susam_Altun_An_Efficient_Algorithm_to_Synthesize_Quantum_Circuits_and_Optimization.pptx Slides]
+
<br> [http://www.ecc.itu.edu.tr/images/d/d6/Vahapoglu_Altun_Accurate_Synthesis_of_Arithmetic_Operations_with_Stochastic_Logic.pptx Poster]
 
|}
 
|}
-->
 
 
|}
 
|}
  
Line 444: Line 613:
 
| width="696" |'''Funding Projects'''
 
| width="696" |'''Funding Projects'''
 
|}
 
|}
 +
 
{| style="margin-left: auto; margin-right: 0px; border:1px solid #abd5f5; background:#f1f5fc;"
 
{| style="margin-left: auto; margin-right: 0px; border:1px solid #abd5f5; background:#f1f5fc;"
  
Line 450: Line 620:
 
|- valign="top"
 
|- valign="top"
 
| width="140" |'''title''':
 
| width="140" |'''title''':
| width="558"|Implementation of a Fault-Aware 8-Bit Reversible Microprocessor
+
| width="558"|Implementation of Accurate Stochastic Circuit Blocks and their Applications for Printed/Flexible Electronic Systems
 
|- valign="top"
 
|- valign="top"
 
| '''agency & program''':
 
| '''agency & program''':
| [http://www.tubitak.gov.tr/tr/destekler/akademik/ulusal-destek-programlari/icerik-1002-hizli-destek-programi TUBITAK Short Term R&D Funding Program (1002)]
+
| [http://www.tubitak.gov.tr/tr/destekler/akademik/ulusal-destek-programlari/icerik-1001-bilimsel-ve-teknolojik-arastirma-projelerini-destekleme-pr TUBITAK Scientific and Technological Research Projects Funding Program (1001)]
 
|- valign="top"
 
|- valign="top"
 
| '''budget''':
 
| '''budget''':
| 30.000 TL
+
| 260.000 TL
 
|- valign="top"
 
|- valign="top"
 
| '''duration''':
 
| '''duration''':
| 2016-2017, ''completed''
+
| 2017-2020
 
|}
 
|}
 
{| style="margin-left: auto; margin-right: 0px; border:0.1px solid #abd5ff; background:#f1f5fc; padding:0.2em 0em;"
 
{| style="margin-left: auto; margin-right: 0px; border:0.1px solid #abd5ff; background:#f1f5fc; padding:0.2em 0em;"
 
|- valign="top"
 
|- valign="top"
 
| width="140" |'''project goal''':
 
| width="140" |'''project goal''':
| width="558"| Developing a synthesis methodology for online fault aware reversible circuits and implementing their CMOS counterparts.
+
| width="558"| Improving accuracy in stochastic computing with implementing error–free aritmetic blocks, and using them in large-area electronics.  
  
|}
+
|}  
 
|}
 
|}
 
 
<!-- {| style="margin-left: auto; margin-right: 0px; border:1px solid #abd5f5; background:#f1f5fc;"
 
<!-- {| style="margin-left: auto; margin-right: 0px; border:1px solid #abd5f5; background:#f1f5fc;"
  
Line 475: Line 644:
 
|- valign=top
 
|- valign=top
 
| width="140" |'''title''':
 
| width="140" |'''title''':
| width="558"|Quantum Circuit Design and Computation
+
| width="558"| Gate and Transistor Implementations of Accurate Arithmetic Operation Blocks with Stochastic Logic
 
|- valign="top"
 
|- valign="top"
 
| '''agency & program''':
 
| '''agency & program''':
Line 481: Line 650:
 
|- valign="top"
 
|- valign="top"
 
| '''duration''':
 
| '''duration''':
| 2014-2015, ''completed''
+
| 2017-2019
 
|}
 
|}
 
   
 
   
 
|} -->
 
|} -->
 
 
|}
 
|}
 
|}
 
|}
Line 491: Line 659:
  
  
<!--        STOCHASTIC      -->
+
<!--        APPROXIMATE      -->
  
 
{| id=portal cellspacing="0" cellpadding="0" width=100% style="border:1px solid #B8C7D9; padding:0px;"
 
{| id=portal cellspacing="0" cellpadding="0" width=100% style="border:1px solid #B8C7D9; padding:0px;"
 
|-
 
|-
| colspan="2" style="background:#8FBCAF; text-align:center; padding:1px; border-bottom:1px #8FBCAF solid;" |
+
| colspan="2" style="background:#8FBC7F; text-align:center; padding:1px; border-bottom:1px #8FBC7F solid;" |
<h2 style="margin:.1em; border-bottom:1px; font-size:140%; font-weight:bold;"> Stochastic Circuit Design </h2>
+
<h2 style="margin:.1em; border-bottom:1px; font-size:140%; font-weight:bold;"> Approximate Circuit and System Design </h2>
 
|-
 
|-
 
| valign="top" style="padding:8px 8px 0px 8px; background:#f5fffa;" <!--H210 S4 V100--> |
 
| valign="top" style="padding:8px 8px 0px 8px; background:#f5fffa;" <!--H210 S4 V100--> |
 +
<!-- <h3>
 +
Power/Area Efficient Approximate System Design Methodology</h3> -->
  
<h3>
+
This work provides '''power/area efficiency of circuit-level design with accuracy supervision of system-level design'''. First, approximate computational units, mostly adders and multipliers, are synthesized in circuit level. Then, in system level, the appropriate approximate computational units are selected to minimize the total computation cost, yet maintaining
Accurate Arithmetic Implementations</h3>
+
the ultimate performance. The method investigates the overall system from the highest level down to the arithmetic units to determine the sufficient output quality at each block.
  
We propose a method to overcome the main drawback in stochastic computing, '''low accuracy''' or related '''long computing times'''. Our method manipulates stochastic bit streams with the aid of feedback mechanisms. We implement error-free arithmetic multiplier and adder circuits by considering performance parameters area, delay, and accuracy.
+
[[Image:Research-approximate.png|center|none|800px|link=]]
 
+
[[Image:Research-stochastic-1.png|center|none|800px|link=]]
+
  
 
<!--        YAYIN      -->
 
<!--        YAYIN      -->
Line 521: Line 689:
 
{| style="border:1px solid #abd5f5; background:#f1f5fc;"
 
{| style="border:1px solid #abd5f5; background:#f1f5fc;"
 
|
 
|
{|
+
{|  
 
|- valign=top
 
|- valign=top
 
| width="100" |'''title''':
 
| width="100" |'''title''':
| width="450"|[[Media:Vahapoglu_Altun_Accurate_Synthesis_of_Arithmetic_Operations_with_Stochastic_Logic.pdf | Accurate Synthesis of Arithmetic Operations with Stochastic Logic]]
+
| width="450"|[[Media:Nojehdeh_Altun_Approximate_Adders_Multipliers.pdf | Systematic Synthesis of Approximate Adders and Multipliers with Accurate Error Calculations]]
 
|- valign="top"
 
|- valign="top"
 
| '''authors''':
 
| '''authors''':
| Ensar Vahapoglu and [[Mustafa Altun]]
+
| Mohammadreza Nojehdeh and [[Mustafa Altun]]
 +
|- valign="top"
 +
| '''appeared&nbsp;in''':
 +
| width="450" | [http://www.journals.elsevier.com/integration Integration, the VLSI Journal], Vol. 70, pp. 99&ndash;107, 2020.
 
|- valign=top
 
|- valign=top
 
| '''presented&nbsp;at''':
 
| '''presented&nbsp;at''':
| width="450"| [http://www.isvlsi.org/ IEEE Computer Society Annual Symposium on VLSI (ISVLSI)], Pittsburgh, USA, 2016.
+
| width="450"| [http://www.isvlsi.org/ IEEE Computer Society Annual Symposium on VLSI (ISVLSI)], Limassol, Cyprus, 2020.
 
|}
 
|}
| align=center width="70" |
+
| align=center width="70" |  
 
<span class="plainlinks">
 
<span class="plainlinks">
[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/d/d6/Vahapoglu_Altun_Accurate_Synthesis_of_Arithmetic_Operations_with_Stochastic_Logic.pdf]]</span>
+
[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/c/c8/Nojehdeh_Altun_Approximate_Adders_Multipliers.pdf]]</span>
 
<br>
 
<br>
[[Media:Vahapoglu_Altun_Accurate_Synthesis_of_Arithmetic_Operations_with_Stochastic_Logic.pdf | Paper]]
+
[[Media:Nojehdeh_Altun_Approximate_Adders_Multipliers.pdf | Paper]]
| align="center" width="70" |
+
| align="center" width="70" |  
 
<span class="plainlinks">
 
<span class="plainlinks">
  
[[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/d/d6/Vahapoglu_Altun_Accurate_Synthesis_of_Arithmetic_Operations_with_Stochastic_Logic.pptx]]
+
[[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/7/7f/Nojehdeh_Aksoy_Altun_Approximate_ANN.pptx]]
 
</span>
 
</span>
<br> [http://www.ecc.itu.edu.tr/images/d/d6/Vahapoglu_Altun_Accurate_Synthesis_of_Arithmetic_Operations_with_Stochastic_Logic.pptx Poster]
+
<br> [http://www.ecc.itu.edu.tr/images/7/7f/Nojehdeh_Aksoy_Altun_Approximate_ANN.pptx Slides]
 
|}
 
|}
 +
{| style="border:1px solid #abd5f5; background:#f1f5fc;"
 +
|
 +
{|
 +
|- valign=top
 +
| width="100" |'''title''':
 +
| width="450"|[[Media:Ayhan_Altun_Circuit_Aware_Approximate_System_Design.pdf| Circuit Aware Approximate System Design with Case Studies in Image Processing and Neural Networks]]
 +
|- valign="top"
 +
| '''authors''':
 +
| Tuba Ayhan and [[Mustafa Altun]]
 +
|- valign="top"
 +
| '''appeared&nbsp;in''':
 +
| [http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=6287639 IEEE Access], Vol. 7, pp. 4726&ndash;4734, 2019.
 +
|- valign=top
 +
| '''presented&nbsp;at''':
 +
| width="450"| [http://www.isvlsi.org/ IEEE Computer Society Annual Symposium on VLSI (ISVLSI)], Bochum, Germany, 2017.
 +
|}
 +
 +
| align=center width="70" |
 +
<span class="plainlinks">
 +
[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/9/90/Ayhan_Altun_Circuit_Aware_Approximate_System_Design.pdf]]</span>
 +
<br>
 +
[[Media:Ayhan_Altun_Circuit_Aware_Approximate_System_Design.pdf | Paper]]
 +
| align="center" width="70" |
 +
<span class="plainlinks">
 +
 +
[[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/8/86/Ayhan_Kula_Altun_Approximate_System_Design_Methodology.pptx]]
 +
</span>
 +
<br> [http://www.ecc.itu.edu.tr/images/8/86/Ayhan_Kula_Altun_Approximate_System_Design_Methodology.pptx Slides]
 +
|}
 +
 
|}
 
|}
  
Line 565: Line 766:
 
|- valign="top"
 
|- valign="top"
 
| width="140" |'''title''':
 
| width="140" |'''title''':
| width="558"|Implementation of Accurate Stochastic Circuit Blocks and their Applications for Printed/Flexible Electronic Systems
+
| width="558"|Design of Reconfigurable Circuits and Systems that can Perform Approximate Computation and their Use in Image Processing Applications Involving Learning
 
|- valign="top"
 
|- valign="top"
 
| '''agency & program''':
 
| '''agency & program''':
Line 571: Line 772:
 
|- valign="top"
 
|- valign="top"
 
| '''budget''':
 
| '''budget''':
| 260.000 TL
+
| 230.000 TL
 
|- valign="top"
 
|- valign="top"
 
| '''duration''':
 
| '''duration''':
| 2017-2020
+
| 2017-2020, ''completed''
 
|}
 
|}
 
{| style="margin-left: auto; margin-right: 0px; border:0.1px solid #abd5ff; background:#f1f5fc; padding:0.2em 0em;"
 
{| style="margin-left: auto; margin-right: 0px; border:0.1px solid #abd5ff; background:#f1f5fc; padding:0.2em 0em;"
 
|- valign="top"
 
|- valign="top"
 
| width="140" |'''project goal''':
 
| width="140" |'''project goal''':
| width="558"| Improving accuracy in stochastic computing with implementing error–free aritmetic blocks, and using them in large-area electronics.  
+
| width="558"| Developing a hierarchical circuit/system design approach that can find solutions close to optimal solutions for power/energy consumption by determining the required accuracy performance of each circuit block, depending on the level of accuracy or quality desired from the system.
 
+
|}
+
 
|}
 
|}
 
{| style="margin-left: auto; margin-right: 0px; border:1px solid #abd5f5; background:#f1f5fc;"
 
 
|
 
{|
 
|- valign=top
 
| width="140" |'''title''':
 
| width="558"| Gate and Transistor Implementations of Accurate Arithmetic Operation Blocks with Stochastic Logic
 
|- valign="top"
 
| '''agency & program''':
 
| [http://bap.itu.edu.tr/ Istanbul Technical University Research Support Program (ITU-BAP)]
 
|- valign="top"
 
| '''duration''':
 
| 2017-2019
 
 
|}
 
|}
 
|}
 
 
 
|}
 
|}
 
|}
 
|}
 
|}
 
|}
  
 
+
<!--        QUANTUM      -->
<!--        APPROXIMATE      -->
+
  
 
{| id=portal cellspacing="0" cellpadding="0" width=100% style="border:1px solid #B8C7D9; padding:0px;"
 
{| id=portal cellspacing="0" cellpadding="0" width=100% style="border:1px solid #B8C7D9; padding:0px;"
 
|-
 
|-
| colspan="2" style="background:#8FBC9F; text-align:center; padding:1px; border-bottom:1px #8FBCAF solid;" |
+
| colspan="2" style="background:#8FBC6F; text-align:center; padding:1px; border-bottom:1px #8FBC6F solid;" |
<h2 style="margin:.1em; border-bottom:1px; font-size:140%; font-weight:bold;"> Approximate Circuit and System Design </h2>
+
<h2 style="margin:.1em; border-bottom:1px; font-size:140%; font-weight:bold;"> Reversible Computing </h2>
 
|-
 
|-
 
| valign="top" style="padding:8px 8px 0px 8px; background:#f5fffa;" <!--H210 S4 V100--> |
 
| valign="top" style="padding:8px 8px 0px 8px; background:#f5fffa;" <!--H210 S4 V100--> |
 +
 +
Unlike conventional CMOS circuits, reversible circuits do not have latent faults, so faults occurring in internal circuit nodes
 +
always result in an error at the output. This is a unique feature for online or concurrent fault tolerance. Motivated by this, we implement error tolerant CMOS circuit blocks by exploiting reversible computing.  We first synthesize reversible circuits with reversible gates; then we make them fault-tolerant; and  finally we perform conversion from reversible gates to CMOS gates.
 +
 +
 +
[[Image:Research-reversible-2.png|center|none|800px|link=]]
  
 
<h3>
 
<h3>
Power/Area Efficient Approximate System Design Methodology</h3>
 
  
This work provides '''power/area efficiency of circuit-level design with accuracy supervision of system-level design'''. The proposed
+
Perfect Online Error Detection </h3>
method selects approximate computational units that minimize the total computation cost, yet maintaining
+
the ultimate performance. The method investigates the overall system from the highest level down to the arithmetic units to determine the sufficient output quality at each block.
+
  
[[Image:Research-approximate.png|center|none|800px|link=]]
+
In order to achieve a CMOS circuit having '''100% online or concurrent error detection''', we exploit reversible computing by proposing a new, fault preservative, and reversible gate library. We ensure that the parity, even or odd, is preserved at all levels including the output level unless there is a faulty node.
 +
<!--<h3>
  
 +
Synthesis </h3>
 +
 +
We propose a fast synthesis algorithm that implements any given reversible Boolean function with reversible gates. Instead of an exhaustive search on every given function, our algorithm creates a library of '''essential functions''' and performs '''sorting'''. As an example, to implement 4 bit circuits we only use 120 essential functions out of all 20922789888000 functions. We also perform optimization for both '''reversible and quantum circuit costs''' by considering adjacent gate pairs.
 +
-->
 +
<h3>
 +
 +
Online Error Detection and Correction </h3>
 +
 +
We develop two techniques to make a reversible circuit fault-tolerant by using multiple-control Toffoli gates. The first technique is based on '''single parity preserving''', and offers error detection for odd number of errors at the output. The second technique is constructed on '''Hamming codes for error correction'''. We also claim that perfect error detection is possible with conservative reversible gates such as a Fredkin gate. As the next step, we '''utilize the proposed reversible circuits with conventional CMOS gates'''.
 +
 +
<!-- [[Image:Research-4.png|center|none|800px|link=]] -->
 
<!--        YAYIN      -->
 
<!--        YAYIN      -->
 
{| id="mp-upper" style="width: 100%; margin:4px 0 0 0; background:none; border-spacing: 0px;"
 
{| id="mp-upper" style="width: 100%; margin:4px 0 0 0; background:none; border-spacing: 0px;"
Line 636: Line 832:
 
| width="696" |'''Selected Publications'''
 
| width="696" |'''Selected Publications'''
 
|}
 
|}
 +
 
{| style="border:1px solid #abd5f5; background:#f1f5fc;"
 
{| style="border:1px solid #abd5f5; background:#f1f5fc;"
 +
 
|
 
|
 
{|  
 
{|  
 
|- valign=top
 
|- valign=top
 
| width="100" |'''title''':
 
| width="100" |'''title''':
| width="450"|[[Media:Ayhan_Altun_Circuit_Aware_Approximate_System_Design.pdf| Circuit Aware Approximate System Design with Case Studies in Image Processing and Neural Networks]]
+
| width="450"|[[Media:Parvin_Altun_Perfect_Concurrent_Fault_Detection.pdf| Perfect Concurrent Fault Detection in CMOS Logic Circuits Using Parity Preservative Reversible Gates
 +
]]
 
|- valign="top"
 
|- valign="top"
 
| '''authors''':
 
| '''authors''':
| Tuba Ayhan and [[Mustafa Altun]]
+
| Sajjad Parvin and [[Mustafa Altun]]
 
|- valign="top"
 
|- valign="top"
 
| '''appeared&nbsp;in''':
 
| '''appeared&nbsp;in''':
| [http://ieeeaccess.ieee.org/ IEEE Access], Vol. 7, pp. 4726&ndash;4734, 2019.
+
| [http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=6287639 IEEE Access], Vol. 7, pp. 163939&ndash;163947, 2019.
 
|- valign=top
 
|- valign=top
 
| '''presented&nbsp;at''':
 
| '''presented&nbsp;at''':
| width="450"| [http://www.isvlsi.org/ IEEE Computer Society Annual Symposium on VLSI (ISVLSI)], Bochum, Germany, 2017.
+
| width="450"| [http://tima.univ-grenoble-alpes.fr/conferences/iolts/iolts19/ IEEE International Symposium on On-Line Testing and Robust System Design (IOLTS)], Rhodes Island, Greece, 2019.
 
|}
 
|}
  
 
| align=center width="70" |  
 
| align=center width="70" |  
 
<span class="plainlinks">
 
<span class="plainlinks">
[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/9/90/Ayhan_Altun_Circuit_Aware_Approximate_System_Design.pdf]]</span>
+
[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/3/3c/Parvin_Altun_Perfect_Concurrent_Fault_Detection.pdf]]</span>
 
<br>
 
<br>
[[Media:Ayhan_Altun_Circuit_Aware_Approximate_System_Design.pdf | Paper]]
+
[[Media:Parvin_Altun_Perfect_Concurrent_Fault_Detection.pdf | Paper]]
 
| align="center" width="70" |  
 
| align="center" width="70" |  
 
<span class="plainlinks">
 
<span class="plainlinks">
  
[[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/8/86/Ayhan_Kula_Altun_Approximate_System_Design_Methodology.pptx]]
+
[[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/f/f4/Parvin_Altun_CMOS_Fault_Tolerance_with_Preservative_Reversible_Gates.pptx]]
 
</span>
 
</span>
<br> [http://www.ecc.itu.edu.tr/images/8/86/Ayhan_Kula_Altun_Approximate_System_Design_Methodology.pptx Slides]
+
<br> [http://www.ecc.itu.edu.tr/images/f/f4/Parvin_Altun_CMOS_Fault_Tolerance_with_Preservative_Reversible_Gates.pptx Poster]
 
|}
 
|}
  
 +
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 +
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 +
|- valign=top
 +
| width="100" |'''title''':
 +
| width="524"|[[Media:Altun_Parvin_Cilasun_Exploiting_Reversible_Computing_for_CMOS_Fault_Tolerance.pdf| Exploiting Reversible Computing for Latent-Fault-Free Error Detecting/Correcting CMOS Circuits
 +
]]
 +
|- valign="top"
 +
| '''authors''':
 +
| [[Mustafa Altun]], Sajjad Parvin, and Husrev Cilasun
 +
|- valign="top"
 +
| '''appeared&nbsp;in''':
 +
| [http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=6287639 IEEE Access], Vol. 6, pp. 74475&ndash;74484, 2018.
 +
|}
 +
| align=center width="70" |
 +
<span class="plainlinks">
 +
[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/7/7d/Altun_Parvin_Cilasun_Exploiting_Reversible_Computing_for_CMOS_Fault_Tolerance.pdf]]</span>
 +
<br>
 +
[[Media:Altun_Parvin_Cilasun_Exploiting_Reversible_Computing_for_CMOS_Fault_Tolerance.pdf | Paper]]
 +
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 +
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 +
| width="100" |'''title''':
 +
| width="450"|[[Media:Susam_Altun_Fast_Synthesis_of_Reversible_Circuits_using_a_Sorting_Algorithm_and_Optimization.pdf| Fast Synthesis of Reversible Circuits using a Sorting Algorithm and Optimization]]
 +
|- valign="top"
 +
| '''authors''':
 +
| Omercan Susam and [[Mustafa Altun]]
 +
|- valign="top"
 +
| '''appeared&nbsp;in''':
 +
| width="450"| [http://www.oldcitypublishing.com/journals/mvlsc-home/ Journal of Multiple-Valued Logic and Soft Computing], Vol. 29, Issue 1-2, pp. 1&ndash;23, 2017.
 +
|- valign="top"
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| '''presented&nbsp;at''':
 +
| width="450"| [http://www.ieee-icecs2014.org/ IEEE International Conference on Electronics Circuits and Systems (ICECS)], Marseille, France, 2014.
 +
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 +
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 +
[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/c/cd/Susam_Altun_Fast_Synthesis_of_Reversible_Circuits_using_a_Sorting_Algorithm_and_Optimization.pdf]]</span>
 +
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 +
[[Media:Susam_Altun_Fast_Synthesis_of_Reversible_Circuits_using_a_Sorting_Algorithm_and_Optimization.pdf | Paper]]
 +
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 +
<span class="plainlinks">
 +
 +
[[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/d/d0/Susam_Altun_An_Efficient_Algorithm_to_Synthesize_Quantum_Circuits_and_Optimization.pptx]]
 +
</span>
 +
<br> [http://www.ecc.itu.edu.tr/images/d/d0/Susam_Altun_An_Efficient_Algorithm_to_Synthesize_Quantum_Circuits_and_Optimization.pptx Slides]
 +
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| width="696" |'''Funding Projects'''
 
| width="696" |'''Funding Projects'''
 
|}
 
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|- valign="top"
 
| width="140" |'''title''':
 
| width="140" |'''title''':
| width="558"|Design of Reconfigurable Circuits and Systems that can Perform Approximate Computation and their Use in Image Processing Applications Involving Learning
+
| width="558"|Implementation of a Fault-Aware 8-Bit Reversible Microprocessor
 
|- valign="top"
 
|- valign="top"
 
| '''agency & program''':
 
| '''agency & program''':
| [http://www.tubitak.gov.tr/tr/destekler/akademik/ulusal-destek-programlari/icerik-1001-bilimsel-ve-teknolojik-arastirma-projelerini-destekleme-pr TUBITAK Scientific and Technological Research Projects Funding Program (1001)]
+
| [http://www.tubitak.gov.tr/tr/destekler/akademik/ulusal-destek-programlari/icerik-1002-hizli-destek-programi TUBITAK Short Term R&D Funding Program (1002)]
 
|- valign="top"
 
|- valign="top"
 
| '''budget''':
 
| '''budget''':
| 230.000 TL
+
| 30.000 TL
 
|- valign="top"
 
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| '''duration''':
 
| '''duration''':
| 2017-2020
+
| 2016-2017, ''completed''
 
|}
 
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{| style="margin-left: auto; margin-right: 0px; border:0.1px solid #abd5ff; background:#f1f5fc; padding:0.2em 0em;"
 
{| style="margin-left: auto; margin-right: 0px; border:0.1px solid #abd5ff; background:#f1f5fc; padding:0.2em 0em;"
 
|- valign="top"
 
|- valign="top"
 
| width="140" |'''project goal''':
 
| width="140" |'''project goal''':
| width="558"| Developing a hierarchical circuit/system design approach that can find solutions close to optimal solutions for power/energy consumption by determining the required accuracy performance of each circuit block, depending on the level of accuracy or quality desired from the system.
+
| width="558"| Developing a synthesis methodology for online fault aware reversible circuits and implementing their CMOS counterparts.
 +
 
 +
|} 
 
|}
 
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 +
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| width="140" |'''title''':
 +
| width="558"|Quantum Circuit Design and Computation
 +
|- valign="top"
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| '''agency & program''':
 +
| [http://bap.itu.edu.tr/ Istanbul Technical University Research Support Program (ITU-BAP)]
 +
|- valign="top"
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| '''duration''':
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| 2014-2015, ''completed''
 
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<h2 style="margin:.1em; border-bottom:1px; font-size:140%; font-weight:bold;"> Reliability of Electronic Products </h2>
 
<h2 style="margin:.1em; border-bottom:1px; font-size:140%; font-weight:bold;"> Reliability of Electronic Products </h2>
 
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We investigate different degradation mechanisms of ZnO varistors. We propose a model showing how the varistor voltage Vv changes by time for different stress levels. For this purpose, accelerated degradation tests are applied for different AC current levels; then voltage values are measured. Different from the common practice in the literature that considers a degradation with only decreasing Vv values, we demonstrate '''either an increasing or a decreasing trend in the Vv parameter'''.
 
We investigate different degradation mechanisms of ZnO varistors. We propose a model showing how the varistor voltage Vv changes by time for different stress levels. For this purpose, accelerated degradation tests are applied for different AC current levels; then voltage values are measured. Different from the common practice in the literature that considers a degradation with only decreasing Vv values, we demonstrate '''either an increasing or a decreasing trend in the Vv parameter'''.
 
+
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<h3>
 
Calibrated Accelerated Life Testing</h3>
 
Calibrated Accelerated Life Testing</h3>
  
Dramatic decrease in failure rates for electronic products makes conventional accelerated life tests ('''ALT''') extremely time consuming and costly. Recently proposed calibrated accelerated life tests ('''CALT''') aim to use fewer samples than those used in ALT.  We thoroughly compare ALT and CALT by considering the effects of failure rate, acceleration factor, and stress level on the required test time.
+
Dramatic decrease in failure rates for electronic products makes conventional accelerated life tests ('''ALT''') extremely time consuming and costly. Recently proposed calibrated accelerated life tests ('''CALT''') aim to use fewer samples than those used in ALT.  We thoroughly compare ALT and CALT by considering the effects of failure rate, acceleration factor, and stress level on the required test time.-->
  
 
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[[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/d/de/Yadavari_EtAl_Effects_of_ZnO_Varistor_Degradation_on_the_Overvoltage_Protection_Mechanism_of_Electronic_Boards.pptx]]
 
</span>
 
</span>
 
<br> [http://www.ecc.itu.edu.tr/images/d/de/Yadavari_EtAl_Effects_of_ZnO_Varistor_Degradation_on_the_Overvoltage_Protection_Mechanism_of_Electronic_Boards.pptx Slides]
 
<br> [http://www.ecc.itu.edu.tr/images/d/de/Yadavari_EtAl_Effects_of_ZnO_Varistor_Degradation_on_the_Overvoltage_Protection_Mechanism_of_Electronic_Boards.pptx Slides]
 
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<br> [http://www.ecc.itu.edu.tr/images/a/a8/Sal_Altun_Extensive_Investigation_of_CALT_in_Comparison_with_ALT.pptx Slides]
 
<br> [http://www.ecc.itu.edu.tr/images/a/a8/Sal_Altun_Extensive_Investigation_of_CALT_in_Comparison_with_ALT.pptx Slides]
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<h2 style="margin:.1em; border-bottom:1px; font-size:140%; font-weight:bold;"> Analog Circuit Design </h2>
 
<h2 style="margin:.1em; border-bottom:1px; font-size:140%; font-weight:bold;"> Analog Circuit Design </h2>
 
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<h2 style="margin:.1em; border-bottom:1px; font-size:140%; font-weight:bold;"> Discrete Mathematics </h2>
 
<h2 style="margin:.1em; border-bottom:1px; font-size:140%; font-weight:bold;"> Discrete Mathematics </h2>
 
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|-

Latest revision as of 14:02, 21 October 2020

Our research aims to develop novel ways of computing, circuit design, and reliability for electronic circuits and systems. Our research mainly targets emerging technologies and new computing paradigms. Listed below are the research topics, ordered from newest to oldest as well as by considering their importance. Each topic is explained briefly in support with related papers and projects.

Contents

Computing with Switching Lattices

A switching lattice, formed as a two dimensional network of four-terminal switches, is introduced as a crossbar based, regular, dense, area-efficient, and CMOS-compatible structure for logic computing. A four-terminal switch, corresponding to a crossbar cross-point or a lattice site, has one control input and four terminals. The control input makes all of its terminals either all disconnected (OFF) or all connected (ON).

Research lattice logic.png

Technology Development

We show that switching lattices are CMOS-compatible. For this purpose, we propose different four-terminal switch structures, and construct them in three dimensional technology computer-aided design (TCAD) environment as well as in Cadence environment satisfying the design rules of the TSMC 65nm CMOS process and perform simulations. Experimental results show that the realization of logic functions using switching lattices occupy much less layout area and have competitive delay and power consumption values when compared to the conventional CMOS implementations.

Research lattice technology.png

Performance Optimization

We propose a logic synthesis algorithm to optimize lattice sizes under a delay constraint. We also propose static and dynamic logic solutions for area-delay-power efficiency of the lattices.

Synthesis

We propose optimal and heuristic algorithms to implement logic functions with minimum size switching lattices.

Selected Publications
title: Technology Development and Modeling of Switching Lattices Using Square and H Shaped Four-Terminal Switches
authors: Nihat Akkan, Serzat Safaltin, Levent Aksoy, Ismail Cevik, Herman Sedef, Csaba Andras Moritz, and Mustafa Altun
appeared in: IEEE Transactions on Emerging Topics in Computing, early access, 2020.
presented at: Design, Automation and Test in Europe (DATE), Grenoble, France, 2020.

PDF.png
Paper

PPT.jpg
Slides

title: Novel Methods for Efficient Realization of Logic Functions Using Switching Lattices
authors: Levent Aksoy and Mustafa Altun
appeared in: IEEE Transactions on Computers, Vol. 69, Issue 3, pp. 427–440, 2020.
presented at: Design, Automation and Test in Europe (DATE), Florence, Italy, 2019.

PDF.png
Paper

PPT.jpg
Slides

Funding Projects
title: Implementation of 3D Nano Stuctures and Switching Lattices
agency & program: TUBITAK-NSF Joint Research Program (2501)
budget: 720.000 TL
duration: 2019-2022
project goal: Design, fabrication, and test of switching lattices and nano-crossbars within 3D interconnect architectures.


Energy Efficient ANN Hardware Implementation

We aim to use hardware aware training techniques, new hybrid bit parallel-serial number representations, and constant multiplication based sharing techniques to reduce energy consumption of feed-forward artificial neural networks (ANNs).

Research ANN.png


Selected Publications
title: Efficient Time-Multiplexed Realization of Feedforward Artificial Neural Networks
authors: Levent Aksoy, Sajjad Parvin, Mohammadreza Nojehdeh, and Mustafa Altun
presented at: IEEE International Symposium on Circuits and Systems (ISCAS), Seville, Spain, 2020.

PDF.png
Paper

PPT.jpg
Slides

Funding Projects
title: Energy-Efficient Hardware Design of Artificial Neural Networks (ANNs) for Mobile Platforms
agency & program: TUBITAK Scientific and Technological Research Projects Funding Program (1001)
budget: 400.000 TL
duration: 2020-2023
project goal: Implementing energy-efficient ANNs by changing the rules of computing from the level of number representations to the level of circuit and system design.


Computing with Nano-Crossbar Arrays

Nano-crossbar arrays have emerged as a strong candidate technology to replace CMOS in near future. They are regular and dense structures. Computing with crossbar arrays is achieved by its crosspoints behaving as switches, either two-terminal or four-terminal. Depending on the technology used, a two-terminal switch behaves as a diode, a resistive/memristive switch, or a field effect transistor (FET). On the other hand, a four-terminal switch has a unique behavior. While there have been many different technologies proposed for two-terminal switch based arrays, technology development for four-terminal switch based arrays, called switching lattices, has recently started.

For both two-terminal and four-terminal switch based arrays, we aim to develop a complete synthesis and performance optimization methodology for switching nano-crossbar arrays that leads to the design and construction of an emerging nanocomputer. We also aim to develeop CMOS-compatible technologies for crossbar arrays, specifically for switching lattices.

Research nano-2019.png

Technology Development

Although a four-terminal switch based array offers a significant area advantage, in terms of the number of switches, compared to the ones having two-terminal switches, its realization at the technology level needs further justifications and raises a number of questions about its feasibility. We answer these questions. By using three dimensional technology computer-aided design (TCAD) simulations, we show that four-terminal switches can be directly implemented with the CMOS technology. Then, by fitting the TCAD simulation data to the standard CMOS current-voltage equations, we develop a Spice model of a four-terminal switch.

Performance Optimization

We study crossbar arrays including the memristive ones. We propose a defect-tolerant logic synthesis algorithms by considering area, delay, and power costs of the arrays.

Fault Tolerance

We examine reconfigurable crossbar arrays by considering randomly occurred stuck-open and stuck-closed crosspoint faults. In the presence of permanent faults, a fast and accurate heuristic algorithm is proposed that uses the techniques of index sorting, backtracking, and row matching. In the presence of transient faults, tolerance analysis is performed by formally and recursively determining tolerable fault positions.

Synthesis

We study implementation of Boolean functions with nano-crossbar arrays where each crosspoint behaves as a diode, a FET, and a four-terminal switch. For these three types, we give array size formulations for a given Boolean function. Additionally, we focus on four-terminal switch based implementations and propose an algorithm that implements Boolean functions with optimal array sizes.

Selected Publications
title: Realization of Four-Terminal Switching Lattices: Technology Development and Circuit Modeling
authors: Serzat Safaltin, Oguz Gencer, Ceylan Morgul, Levent Aksoy, Sebahattin Gurmen, Csaba Andras Moritz, and Mustafa Altun
presented at: Design, Automation and Test in Europe (DATE), Florence, Italy, 2019.

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Paper

PPT.jpg
Slides

title: Defect Tolerant Logic Synthesis for Memristor Crossbars with Performance Evaluation
authors: Onur Tunali and Mustafa Altun
appeared in: IEEE Micro, Vol. 38, Issue 5, pp. 22–31, 2018.
presented at: Design, Automation and Test in Europe (DATE), Dresden, Germany, 2018.

PDF.png
Paper

PPT.jpg
Slides

title: Logic Synthesis and Testing Techniques for Switching Nano-Crossbar Arrays
authors: Dan Alexandrescu, Mustafa Altun, Lorena Anghel, Anna Bernasconi, Valentina Ciriani, Luca Frontini, and Mehdi Tahoori
appeared in: Microprocessors and Microsystems, Vol. 54, pp. 14–25, 2017.
presented at: Euromicro Conference on Digital System Design (DSD), Limassol, Cyprus, 2016.

PDF.png
Paper

PDF.png
Slides

title: Permanent and Transient Fault Tolerance for Reconfigurable Nano-Crossbar Arrays
authors: Onur Tunali and Mustafa Altun
appeared in: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 36, Issue 5, pp. 747–760, 2017.
presented at: IEEE/ACM International Symposium on Nanoscale Architectures
(NANOARCH)
, Boston, USA, 2015.

PDF.png
Paper

PPT.jpg
Slides

Funding Projects
title: Synthesis and Performance Optimization of a Switching Nano-Crossbar Computer
agency & program: European Union/European Commission H2020 MSCA Research and Innovation Staff Exchange Program (RISE)
budget: 724.500 EURO
duration: 2015-2019, completed
project goal: Developing a complete synthesis methodology for nano-crossbar arrays, and implementing technology-dependent state machines that leads to the design and construction of an emerging computer.
title: Synthesis and Reliability Analysis of Nano Switching Arrays
agency & program: TUBITAK Career Program (3501)
budget: 190.000 TL
duration: 2014-2017, completed
project goal: Performing logic synthesis, fault tolerance, and performance optimization for nano-crossbar arrays.


Stochastic and Bit Stream Computing

We propose a novel computing paradigm “Bit Stream Computing (BSC)” that does not necessarily employ randomly or Binomially distributed bit streams as stochastic computing does. Any type of streams can be used either stochastic or deterministic. The proposed paradigm benefits from the area advantage of stochastic logic and the accuracy advantage of conventional binary logic. We implement accurate arithmetic multiplier and adder circuits, classified as asynchronous or synchronous. We believe that this study opens up new horizons for computing that enables us to implement much smaller yet accurate arithmetic circuits compared to the conventional binary and stochastic ones.

Research Bit Stream.png
Selected Publications
title: From Stochastic to Bit Stream Computing: Accurate Implementation of Arithmetic Circuits and Applications in Neural Networks
authors: Ensar Vahapoglu and Mustafa Altun
appeared in: arXiv, 1805.06262, 2018.
presented at: IEEE Computer Society Annual Symposium on VLSI (ISVLSI), Pittsburgh, USA, 2016.

PDF.png
Paper

PPT.jpg
Poster

Funding Projects
title: Implementation of Accurate Stochastic Circuit Blocks and their Applications for Printed/Flexible Electronic Systems
agency & program: TUBITAK Scientific and Technological Research Projects Funding Program (1001)
budget: 260.000 TL
duration: 2017-2020
project goal: Improving accuracy in stochastic computing with implementing error–free aritmetic blocks, and using them in large-area electronics.


Approximate Circuit and System Design

This work provides power/area efficiency of circuit-level design with accuracy supervision of system-level design. First, approximate computational units, mostly adders and multipliers, are synthesized in circuit level. Then, in system level, the appropriate approximate computational units are selected to minimize the total computation cost, yet maintaining the ultimate performance. The method investigates the overall system from the highest level down to the arithmetic units to determine the sufficient output quality at each block.

Research-approximate.png
Selected Publications
title: Systematic Synthesis of Approximate Adders and Multipliers with Accurate Error Calculations
authors: Mohammadreza Nojehdeh and Mustafa Altun
appeared in: Integration, the VLSI Journal, Vol. 70, pp. 99–107, 2020.
presented at: IEEE Computer Society Annual Symposium on VLSI (ISVLSI), Limassol, Cyprus, 2020.

PDF.png
Paper

PPT.jpg
Slides

title: Circuit Aware Approximate System Design with Case Studies in Image Processing and Neural Networks
authors: Tuba Ayhan and Mustafa Altun
appeared in: IEEE Access, Vol. 7, pp. 4726–4734, 2019.
presented at: IEEE Computer Society Annual Symposium on VLSI (ISVLSI), Bochum, Germany, 2017.

PDF.png
Paper

PPT.jpg
Slides

Funding Projects
title: Design of Reconfigurable Circuits and Systems that can Perform Approximate Computation and their Use in Image Processing Applications Involving Learning
agency & program: TUBITAK Scientific and Technological Research Projects Funding Program (1001)
budget: 230.000 TL
duration: 2017-2020, completed
project goal: Developing a hierarchical circuit/system design approach that can find solutions close to optimal solutions for power/energy consumption by determining the required accuracy performance of each circuit block, depending on the level of accuracy or quality desired from the system.


Reversible Computing

Unlike conventional CMOS circuits, reversible circuits do not have latent faults, so faults occurring in internal circuit nodes always result in an error at the output. This is a unique feature for online or concurrent fault tolerance. Motivated by this, we implement error tolerant CMOS circuit blocks by exploiting reversible computing. We first synthesize reversible circuits with reversible gates; then we make them fault-tolerant; and finally we perform conversion from reversible gates to CMOS gates.


Research-reversible-2.png

Perfect Online Error Detection

In order to achieve a CMOS circuit having 100% online or concurrent error detection, we exploit reversible computing by proposing a new, fault preservative, and reversible gate library. We ensure that the parity, even or odd, is preserved at all levels including the output level unless there is a faulty node.

Online Error Detection and Correction

We develop two techniques to make a reversible circuit fault-tolerant by using multiple-control Toffoli gates. The first technique is based on single parity preserving, and offers error detection for odd number of errors at the output. The second technique is constructed on Hamming codes for error correction. We also claim that perfect error detection is possible with conservative reversible gates such as a Fredkin gate. As the next step, we utilize the proposed reversible circuits with conventional CMOS gates.

Selected Publications
title: Perfect Concurrent Fault Detection in CMOS Logic Circuits Using Parity Preservative Reversible Gates

authors: Sajjad Parvin and Mustafa Altun
appeared in: IEEE Access, Vol. 7, pp. 163939–163947, 2019.
presented at: IEEE International Symposium on On-Line Testing and Robust System Design (IOLTS), Rhodes Island, Greece, 2019.

PDF.png
Paper

PPT.jpg
Poster

title: Exploiting Reversible Computing for Latent-Fault-Free Error Detecting/Correcting CMOS Circuits

authors: Mustafa Altun, Sajjad Parvin, and Husrev Cilasun
appeared in: IEEE Access, Vol. 6, pp. 74475–74484, 2018.

PDF.png
Paper

Funding Projects
title: Implementation of a Fault-Aware 8-Bit Reversible Microprocessor
agency & program: TUBITAK Short Term R&D Funding Program (1002)
budget: 30.000 TL
duration: 2016-2017, completed
project goal: Developing a synthesis methodology for online fault aware reversible circuits and implementing their CMOS counterparts.



Reliability of Electronic Products

The rapid developments in electronics, especially in the last decade, have elevated the importance of electronics reliability. Conventionally used accelerated reliability tests have lost their significance; time consuming and expensive feature of these tests is against the demands of today's very rapid electronic product cycles. In this study, we propose less costly, yet accurate, reliability prediction techniques using field return data, new accelerated test methodologies, and physics of failure based simulations. We cooperate with one of the Europe’s largest household appliance companies Arçelik A.Ş..

Research-3.png

Reliability Analysis and Prediction with Field Data

We propose an accurate reliability prediction model for high-volume electronic products throughout their warranty periods by using field return data. Our model is constructed on a Weibull-exponential hazard rate scheme by using the proposed change point detection method based on backward and forward data analysis. Our prediction model can make a 36-month (full warranty) reliability prediction of an electronic board with using its field data as short as 3 months.

Degradation Processes in Varistors

We investigate different degradation mechanisms of ZnO varistors. We propose a model showing how the varistor voltage Vv changes by time for different stress levels. For this purpose, accelerated degradation tests are applied for different AC current levels; then voltage values are measured. Different from the common practice in the literature that considers a degradation with only decreasing Vv values, we demonstrate either an increasing or a decreasing trend in the Vv parameter.

Selected Publications
title: A Change-Point based Reliability Prediction Model using Field Return Data
authors: Mustafa Altun and Vehbi Comert
appeared in: Reliability Engineering and System Safety, Vol. 156, pp. 175–184, 2016.
presented at: Reliability and Maintainability Symposium (RAMS), Palm Harbor, USA, 2015.

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title: Distinct Degradation Processes in ZnO Varistors: Reliability Analysis and Modeling with Accelerated AC Tests
authors: Hadi Yadavari and Mustafa Altun
appeared in: Turkish Journal of Electrical Engineering and Computer Sciences, Vol. 25, No. 4, pp. 3240–3252, 2017.
presented at: European Safety and Reliability Conference (ESREL), Zurich, Switzerland, 2015.

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Funding Projects
title: An Accurate Reliability Methodology for Appliance Electronic Cards
agency & program: TUBITAK University-Industry Collaboration Grant Program (1505)
budget: 210.000 TL
duration: 2013-2015, completed
project goal: Developing reliability prediction techniques for electronic cards of household appliances by using field return data, new accelerated test methodologies, and physics of failure based simulations.


Analog Circuit Design

Positive Feedback

The conventional wisdom is that analog circuits should not include positive feedback loops. As controversial as it seems, we have successfully used positive feedback for impedance improvement in a current amplifier. With adding few transistors we have achieved very low input resistance values. Additionally, we have proposed a new fully-differential current amplifier and tested it in a filter application.

Selected Publications
title: Design of a Fully Differential Current Mode Operational Amplifier with its Filter Applications
authors: Mustafa Altun and Hakan Kuntman
appeared in: AEU International Journal of Electronics and Communications, Vol. 62, Issue 3, pp. 39–44, 2008.
presented at: ACM Great Lakes Symposium on VLSI (GLSVLSI), Stresa, Italy, 2007.

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Discrete Mathematics

Self Duality Problem

The problem of testing whether a monotone Boolean function in irredundant disjuntive normal form (IDNF) is self-dual is one of few problems in circuit/time complexity whose precise tractability status is unknown. We have focused on this famous problem. We have shown that monotone self-dual Boolean functions in IDNF do not have more variables than disjuncts. We have proposed an algorithm to test whether a monotone Boolean function in IDNF with n variables and n disjuncts is self-dual. The algorithm runs in O(n^3) time.

Selected Publications
title: A Study on Monotone Self-dual Boolean Functions
authors: Mustafa Altun and Marc Riedel
appeared  in: Acta Mathematicae Applicatae Sinica - English Series, Vol. 33, Issue 1, pp. 43–52, 2017.

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