Publications and Presentations

From The Emerging Circuits and Computation Group at ITU
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Listed below are the papers, '''first authored''' by our group members as an indication that the related research is mainly conducted in our group, and the presentations. Research topics are ordered from newest to oldest as well as by considering their importance. Under each topic, papers are ordered from newest to oldest. All materials are subject to copyrights.
 
Listed below are the papers, '''first authored''' by our group members as an indication that the related research is mainly conducted in our group, and the presentations. Research topics are ordered from newest to oldest as well as by considering their importance. Under each topic, papers are ordered from newest to oldest. All materials are subject to copyrights.
 
<div style="float:center; font-size:110%; font-weight:bold; clear:both; padding:0; margin:0.0em;">__TOC__</div>
 
<div style="float:center; font-size:110%; font-weight:bold; clear:both; padding:0; margin:0.0em;">__TOC__</div>
== Computing with Nano-Crossbar Arrays ==
+
 
 +
== Computing with Switching Lattices ==
  
 
=== Technology Development ===
 
=== Technology Development ===
  
 
{| style="border:2px solid #abd5f5; background:#f1f5fc;"
 
{| style="border:2px solid #abd5f5; background:#f1f5fc;"
 
 
|
 
|
{|
+
{|  
 
|- valign=top
 
|- valign=top
 
| width="100" |'''title''':
 
| width="100" |'''title''':
| width="550"|[[Media: Safaltin_EtAl_Technology_Development_for_Switching_Lattices.pdf| Realization of Four-Terminal Switching Lattices: Technology Development and Circuit Modeling]]
+
| width="624"|[[Media:Akkan_EtAl_H_and_Square_Lattice_Technology_Development.pdf | Technology Development and Modeling of Switching Lattices Using Square and H Shaped Four-Terminal Switches]]
 
|- valign="top"
 
|- valign="top"
 
| '''authors''':
 
| '''authors''':
| width="550"| Serzat Safaltin, Oguz Gencer, Ceylan Morgul, Levent Aksoy, Sebahattin Gurmen, Csaba Andras Moritz, and [[Mustafa Altun]]
+
| width="550"| Nihat Akkan, Serzat Safaltin, Levent Aksoy, Ismail Cevik, Herman Sedef, Csaba Andras Moritz, and [[Mustafa Altun]]  
 
|- valign="top"
 
|- valign="top"
| '''presented&nbsp;at''':
+
| '''appeared&nbsp;in''':
| width="550"| [http://www.date-conference.com/ Design, Automation and Test in Europe (DATE)], Florence, Italy, 2019.
+
| [http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=6245516 IEEE Transactions on Emerging Topics in Computing], early access, 2020.
 
|}
 
|}
| align=center width="70" |
+
| align=center width="70" |  
 
<span class="plainlinks">
 
<span class="plainlinks">
[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/2/2c/Safaltin_EtAl_Technology_Development_for_Switching_Lattices.pdf]]</span>
+
[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/6/69/Akkan_EtAl_H_and_Square_Lattice_Technology_Development.pdf]]</span>
 
<br>
 
<br>
[[Media:Safaltin_EtAl_Technology_Development_for_Switching_Lattices.pdf | Paper]]
+
[[Media:Akkan_EtAl_H_and_Square_Lattice_Technology_Development.pdf | Paper]]
| align="center" width="70" |
+
<span class="plainlinks">
+
 
+
[[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/7/71/Safaltin_EtAl_Technology_Development_for_Switching_Lattices.pptx]]
+
</span>
+
<br> [http://www.ecc.itu.edu.tr/images/7/71/Safaltin_EtAl_Technology_Development_for_Switching_Lattices.pptx Slides]
+
 
|}
 
|}
 
=== Comprehensive Performance Optimization===
 
  
 
{| style="border:2px solid #abd5f5; background:#f1f5fc;"
 
{| style="border:2px solid #abd5f5; background:#f1f5fc;"
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|- valign=top
 
|- valign=top
 
| width="100" |'''title''':
 
| width="100" |'''title''':
| width="550"|[[Media: Morgul_EtAl_Integrated_Synthesis_Methodology for_Crossbar_Arrays.pdf | Integrated Synthesis Methodology for Crossbar Arrays]]
+
| width="550"|[[Media:Cevik_Aksoy_Altun_CMOS_Implementation_of_Switching_Lattices.pdf | CMOS Implementation of Switching Lattices]]
 
|- valign="top"
 
|- valign="top"
 
| '''authors''':
 
| '''authors''':
| width="550"| Ceylan Morgul, Luca Frontini, Onur Tunali, Ioana Vatajelu, Valentina Ciriani, Lorena Anghel, Csaba Moritz, Mircea Stan, Dan Alexandrescu, and [[Mustafa Altun]]  
+
| Ismail Cevik, Levent Aksoy, and [[Mustafa Altun]]
 
|- valign="top"
 
|- valign="top"
 
| '''presented&nbsp;at''':
 
| '''presented&nbsp;at''':
| width="550"|[http://www.nanoarch.org/ IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH)], Athens, Greece, 2018.
+
| [http://www.date-conference.com/ Design, Automation, and Test in Europe (DATE)], Grenoble, France, 2020.
 
|}
 
|}
 
| align=center width="70" |  
 
| align=center width="70" |  
 
<span class="plainlinks">
 
<span class="plainlinks">
[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/b/b1/Morgul_EtAl_Integrated_Synthesis_Methodology_for_Crossbar_Arrays.pdf]]</span>
+
[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/5/50/Cevik_Aksoy_Altun_CMOS_Implementation_of_Switching_Lattices.pdf]]</span>
 
<br>
 
<br>
[[Media:Morgul_EtAl_Integrated_Synthesis_Methodology for_Crossbar_Arrays.pdf | Paper]]
+
[[Media:Cevik_Aksoy_Altun_CMOS_Implementation_of_Switching_Lattices.pdf | Paper]]
 
| align="center" width="70" |  
 
| align="center" width="70" |  
 
<span class="plainlinks">
 
<span class="plainlinks">
  
[[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/b/bd/Morgul_EtAl_Integrated_Synthesis_Methodology_for_Crossbar_Arrays.pptx]]
+
[[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/1/1c/Cevik_Aksoy_Altun_CMOS_Implementation_of_Switching_Lattices.pptx]]
 
</span>
 
</span>
<br> [http://www.ecc.itu.edu.tr/images/b/bd/Morgul_EtAl_Integrated_Synthesis_Methodology_for_Crossbar_Arrays.pptx Slides]
+
<br> [http://www.ecc.itu.edu.tr/images/1/1c/Cevik_Aksoy_Altun_CMOS_Implementation_of_Switching_Lattices.pptx Slides]
|}
+
|}  
  
 
{| style="border:2px solid #abd5f5; background:#f1f5fc;"
 
{| style="border:2px solid #abd5f5; background:#f1f5fc;"
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|- valign=top
 
|- valign=top
 
| width="100" |'''title''':
 
| width="100" |'''title''':
| width="550"|[[Media:Tunali_Altun_Logic_Synthesis_and_Defect_Tolerance_for_Memristive_Crossbars.pdf| Logic Synthesis and Defect Tolerance for Memristive Crossbar Arrays]]
+
| width="550"|[[Media: Safaltin_EtAl_Technology_Development_for_Switching_Lattices.pdf| Realization of Four-Terminal Switching Lattices: Technology Development and Circuit Modeling]]
 
|- valign="top"
 
|- valign="top"
 
| '''authors''':
 
| '''authors''':
| Onur Tunali and [[Mustafa Altun]]
+
| width="550"| Serzat Safaltin, Oguz Gencer, Ceylan Morgul, Levent Aksoy, Sebahattin Gurmen, Csaba Andras Moritz, and [[Mustafa Altun]]
 
|- valign="top"
 
|- valign="top"
 
| '''presented&nbsp;at''':
 
| '''presented&nbsp;at''':
| width="550"| [http://www.date-conference.com/ Design, Automation and Test in Europe (DATE)], Dresden, Germany, 2018.
+
| width="550"| [http://www.date-conference.com/ Design, Automation and Test in Europe (DATE)], Florence, Italy, 2019.
 
|}
 
|}
 
| align=center width="70" |
 
| align=center width="70" |
 
<span class="plainlinks">
 
<span class="plainlinks">
[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/5/57/Tunali_Altun_Logic_Synthesis_and_Defect_Tolerance_for_Memristive_Crossbars.pdf]]</span>
+
[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/2/2c/Safaltin_EtAl_Technology_Development_for_Switching_Lattices.pdf]]</span>
 
<br>
 
<br>
[[Media:Tunali_Altun_Logic_Synthesis_and_Defect_Tolerance_for_Memristive_Crossbars.pdf | Paper]]
+
[[Media:Safaltin_EtAl_Technology_Development_for_Switching_Lattices.pdf | Paper]]
 
| align="center" width="70" |
 
| align="center" width="70" |
 
<span class="plainlinks">
 
<span class="plainlinks">
  
[[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/b/b8/Tunali_Altun_Logic_Synthesis_and_Defect_Tolerance_for_Memristive_Crossbars.pptx]]
+
[[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/7/71/Safaltin_EtAl_Technology_Development_for_Switching_Lattices.pptx]]
 
</span>
 
</span>
<br> [http://www.ecc.itu.edu.tr/images/b/b8/Tunali_Altun_Logic_Synthesis_and_Defect_Tolerance_for_Memristive_Crossbars.pptx Slides]
+
<br> [http://www.ecc.itu.edu.tr/images/7/71/Safaltin_EtAl_Technology_Development_for_Switching_Lattices.pptx Slides]
 
|}
 
|}
  
{| style="border:2px solid #abd5f5; background:#f1f5fc;"
+
=== Logic Synthesis and Fault/Variation Tolerance ===
  
 +
{| style="border:2px solid #abd5f5; background:#f1f5fc;"
 
|
 
|
 
{|  
 
{|  
 
|- valign=top
 
|- valign=top
 
| width="100" |'''title''':
 
| width="100" |'''title''':
| width="550"|[[Media:Altun_EtAl_Synthesis_and_Testing_for_Switching_Nano_Crossbar_Arrays.pdf | Logic Synthesis and Testing Techniques for Switching Nano-Crossbar Arrays]]
+
| width="550"|[[Media:Aksoy_Altun_Lattice_Synthesis_for_Complex_Functions.pdf | A Novel Method for the Realization of Complex Logic Functions Using Switching Lattices]]
 
|- valign="top"
 
|- valign="top"
 
| '''authors''':
 
| '''authors''':
| width="550"| Dan Alexandrescu, [[Mustafa Altun]], Lorena Anghel, Anna Bernasconi, Valentina Ciriani, Luca Frontini, and Mehdi Tahoori
+
| Levent Aksoy and [[Mustafa Altun]]
|- valign=top
+
|- valign="top"
| '''appeared&nbsp;in''':
+
| '''presented&nbsp;at''':
| width="624" | [http://www.journals.elsevier.com/microprocessors-and-microsystems/ Microprocessors and Microsystems], Vol. 54, pp. 14&ndash;25, 2017.
+
| [http://iscas2020.org/ IEEE International Symposium on Circuits and Systems (ISCAS)], Seville, Spain, 2020.
 
|}
 
|}
 
| align=center width="70" |  
 
| align=center width="70" |  
 
<span class="plainlinks">
 
<span class="plainlinks">
[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/0/0a/Altun_EtAl_Synthesis_and_Testing_for_Switching_Nano_Crossbar_Arrays.pdf]]</span>
+
[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/7/72/Aksoy_Altun_Lattice_Synthesis_for_Complex_Functions.pdf]]</span>
 
<br>
 
<br>
[[Media:Altun_EtAl_Synthesis_and_Testing_for_Switching_Nano_Crossbar_Arrays.pdf | Paper]]
+
[[Media:Aksoy_Altun_Lattice_Synthesis_for_Complex_Functions.pdf | Paper]]
 +
| align="center" width="70" |
 +
<span class="plainlinks">
  
 +
[[File:MP4.jpg|60px|link=http://www.ecc.itu.edu.tr/images/7/7c/Aksoy_Altun_Lattice_Synthesis_for_Complex_Functions.mp4]]
 +
</span>
 +
<br> [http://www.ecc.itu.edu.tr/images/7/7c/Aksoy_Altun_Lattice_Synthesis_for_Complex_Functions.mp4 Slides]
 
|}
 
|}
  
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|- valign=top
 
|- valign=top
 
| width="100" |'''title''':
 
| width="100" |'''title''':
| width="550"|[[Media:Altun_Ciriani_Tahoori_Computing_with_Nano-Crossbar_Arrays.pdf | Computing with Nano-Crossbar Arrays: Logic Synthesis and Fault Tolerance]]
+
| width="624"|[[Media:Aksoy_Altun_Realizations_with_Switching_Lattices.pdf | Novel Methods for Efficient Realization of Logic Functions Using Switching Lattices]]
 
|- valign="top"
 
|- valign="top"
 
| '''authors''':
 
| '''authors''':
| [[Mustafa Altun]], Valentina Ciriani, and Mehdi Tahoori
+
| Levent Aksoy and [[Mustafa Altun]]  
 
|- valign="top"
 
|- valign="top"
| '''presented&nbsp;at''':
+
| '''appeared&nbsp;in''':
| [http://www.date-conference.com/ Design, Automation and Test in Europe (DATE)], Lausanne, Switzerland, 2017.
+
| [http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12 IEEE Transactions on Computers], Vol. 69, Issue 3, pp. 427&ndash;440, 2020.
 
|}
 
|}
 
| align=center width="70" |  
 
| align=center width="70" |  
 
<span class="plainlinks">
 
<span class="plainlinks">
[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/0/09/Altun_Ciriani_Tahoori_Computing_with_Nano-Crossbar_Arrays.pdf]]</span>
+
[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/e/e0/Aksoy_Altun_Realizations_with_Switching_Lattices.pdf]]</span>
 
<br>
 
<br>
[[Media:Altun_Ciriani_Tahoori_Computing_with_Nano-Crossbar_Arrays.pdf | Paper]]
+
[[Media:Aksoy_Altun_Realizations_with_Switching_Lattices.pdf | Paper]]
| align="center" width="70" |
+
<span class="plainlinks">
+
 
+
[[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/2/28/Altun_Ciriani_Tahoori_Computing_with_Nano-Crossbar_Arrays.pptx]]
+
</span>
+
<br> [http://www.ecc.itu.edu.tr/images/2/28/Altun_Ciriani_Tahoori_Computing_with_Nano-Crossbar_Arrays.pptx Slides]
+
 
|}
 
|}
  
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|
 
|
{|  
+
{|
 
|- valign=top
 
|- valign=top
 
| width="100" |'''title''':
 
| width="100" |'''title''':
| width="550"|[[Media:Altun_EtAl_Synthesis_and_Performance_Optimization_of_a_Switching_Nano-crossbar_Computer.pdf | Synthesis and Performance Optimization of a Switching Nano-crossbar Computer]]
+
| width="550"|[[Media: Aksoy_Altun_SAT_based_Synthesis_of_Switching_Lattices.pdf| A Satisfiability-Based Approximate Algorithm for Logic Synthesis Using Switching Lattices]]
 
|- valign="top"
 
|- valign="top"
 
| '''authors''':
 
| '''authors''':
| width="550"| Dan Alexandrescu, [[Mustafa Altun]], Lorena Anghel, Anna Bernasconi, Valentina Ciriani, and Mehdi Tahoori
+
| Levent Aksoy and [[Mustafa Altun]]
|- valign=top
+
|- valign="top"
 
| '''presented&nbsp;at''':
 
| '''presented&nbsp;at''':
| [http://dsd-seaa2016.cs.ucy.ac.cy/index.php Euromicro Conference on Digital System Design (DSD)], Limassol, Cyprus, 2016.
+
| width="550"| [http://www.date-conference.com/ Design, Automation and Test in Europe (DATE)], Florence, Italy, 2019.
 
|}
 
|}
 
+
| align=center width="70" |
| align=center width="70" |  
+
 
<span class="plainlinks">
 
<span class="plainlinks">
[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/a/ab/Altun_EtAl_Synthesis_and_Performance_Optimization_of_a_Switching_Nano-crossbar_Computer.pdf]]</span>
+
[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/f/fe/Aksoy_Altun_SAT_based_Synthesis_of_Switching_Lattices.pdf]]</span>
 
<br>
 
<br>
[[Media:Altun_EtAl_Synthesis_and_Performance_Optimization_of_a_Switching_Nano-crossbar_Computer.pdf | Paper]]
+
[[Media:Aksoy_Altun_SAT_based_Synthesis_of_Switching_Lattices.pdf | Paper]]
| align="center" width="70" |  
+
| align="center" width="70" |
 
<span class="plainlinks">
 
<span class="plainlinks">
  
[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/7/7f/Altun_EtAl_Synthesis_and_Performance_Optimization_of_a_Switching_Nano-crossbar_Computer_SLIDES.pdf]]
+
[[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/5/54/Aksoy_Altun_SAT_based_Synthesis_of_Switching_Lattices.pptx]]
 
</span>
 
</span>
<br> [[Media:Altun_EtAl_Synthesis_and_Performance_Optimization_of_a_Switching_Nano-crossbar_Computer_SLIDES.pdf | Slides]]
+
<br> [http://www.ecc.itu.edu.tr/images/5/54/Aksoy_Altun_SAT_based_Synthesis_of_Switching_Lattices.pptx Slides]
 
|}
 
|}
  
 
{| style="border:2px solid #abd5f5; background:#f1f5fc;"
 
{| style="border:2px solid #abd5f5; background:#f1f5fc;"
 
 
|
 
|
 
{|  
 
{|  
 
|- valign=top
 
|- valign=top
 
| width="100" |'''title''':
 
| width="100" |'''title''':
| width="550"|[[Media:Morgul_Peker_Altun_Power-Delay-Area_Performance_Modeling_and_Analysis_for_Nano-Crossbar_Arrays.pdf | Power-Delay-Area Performance Modeling and Analysis for Nano-Crossbar Arrays]]
+
| width="624"|[[Media:Morgul_Altun_Algorithms_for_Switching_Lattices.pdf | Optimal and Heuristic Algorithms to Synthesize Lattices of Four-Terminal Switches]]
 
|- valign="top"
 
|- valign="top"
 
| '''authors''':
 
| '''authors''':
| Ceylan Morgul, Furkan Peker, and [[Mustafa Altun]]
+
| Ceylan Morgul and [[Mustafa Altun]]
|- valign=top
+
|- valign="top"
| '''presented&nbsp;at''':
+
| '''appeared&nbsp;in''':
| [http://www.isvlsi.org/ IEEE Computer Society Annual Symposium on VLSI (ISVLSI)], Pittsburgh, USA, 2016.
+
| width="624" | [http://www.journals.elsevier.com/integration Integration, the VLSI Journal], Vol. 64, pp. 60&ndash;70, 2019.
 
|}
 
|}
 
 
| align=center width="70" |  
 
| align=center width="70" |  
 
<span class="plainlinks">
 
<span class="plainlinks">
[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/8/8f/Morgul_Peker_Altun_Power-Delay-Area_Performance_Modeling_and_Analysis_for_Nano-Crossbar_Arrays.pdf]]</span>
+
[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/5/58/Morgul_Altun_Algorithms_for_Switching_Lattices.pdf]]</span>
 
<br>
 
<br>
[[Media:Morgul_Peker_Altun_Power-Delay-Area_Performance_Modeling_and_Analysis_for_Nano-Crossbar_Arrays.pdf | Paper]]
+
[[Media:Morgul_Altun_Algorithms_for_Switching_Lattices.pdf | Paper]]
| align="center" width="70" |
+
<span class="plainlinks">
+
 
+
[[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/5/5a/Morgul_Peker_Altun_Power-Delay-Area_Performance_Modeling_and_Analysis_for_Nano-Crossbar_Arrays.pptx]]
+
</span>
+
<br> [http://www.ecc.itu.edu.tr/images/5/5a/Morgul_Peker_Altun_Power-Delay-Area_Performance_Modeling_and_Analysis_for_Nano-Crossbar_Arrays.pptx Poster]
+
 
|}
 
|}
 
=== Fault/Defect/Variation Tolerance ===
 
  
 
{| style="border:2px solid #abd5f5; background:#f1f5fc;"
 
{| style="border:2px solid #abd5f5; background:#f1f5fc;"
Line 198: Line 179:
 
|- valign=top
 
|- valign=top
 
| width="100" |'''title''':
 
| width="100" |'''title''':
| width="624"|[[Media:Tunali_Morgul_Altun_Defect_Tolerant_Memristor_Crossbars.pdf | Defect Tolerant Logic Synthesis for Memristor Crossbars with Performance Evaluation]]
+
| width="624"|[[Media:Altun_Riedel_Logic_Synthesis_for_Switching_Lattices.pdf | Logic Synthesis for Switching Lattices]]
 
|- valign="top"
 
|- valign="top"
 
| '''authors''':
 
| '''authors''':
| Onur Tunali, Ceylan Morgul, and [[Mustafa Altun]]
+
| [[Mustafa Altun]] and Marc Riedel
 
|- valign="top"
 
|- valign="top"
 
| '''appeared&nbsp;in''':
 
| '''appeared&nbsp;in''':
| width="624" | [http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=40 IEEE Micro], Vol. 38, Issue 5, pp. 22&ndash;31, 2018.
+
| [http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12 IEEE Transactions on Computers], Vol. 61, Issue 11, pp. 1588&ndash;1600, 2012.
 +
<!-- |- valign="top"
 +
| '''presented&nbsp;at''':
 +
| width="624"| [http://fias.uni-frankfurt.de International Conference on Computational Modelling of Nanostructured Materials (ICCMNM)-FIAS], Frankfurt, Germany, 2013. -->
 
|}
 
|}
 
| align=center width="70" |  
 
| align=center width="70" |  
 
<span class="plainlinks">
 
<span class="plainlinks">
[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/d/db/Tunali_Morgul_Altun_Defect_Tolerant_Memristor_Crossbars.pdf]]</span>
+
[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/c/ca/Altun_Riedel_Logic_Synthesis_for_Switching_Lattices.pdf]]</span>
 
<br>
 
<br>
[[Media:Tunali_Morgul_Altun_Defect_Tolerant_Memristor_Crossbars.pdf | Paper]]
+
[[Media:Altun_Riedel_Logic_Synthesis_for_Switching_Lattices.pdf | Paper]]
 
|}
 
|}
  
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|- valign=top
 
|- valign=top
 
| width="100" |'''title''':
 
| width="100" |'''title''':
| width="624"|[[Media:Peker_Altun_Variation_Tolerant_Logic_Mapping_of_Nano_Crossbars.pdf | A Fast Hill Climbing Algorithm for Defect and Variation Tolerant Logic Mapping of Nano-Crossbar Arrays]]
+
| width="624"|[[Media:Altun_Riedel_Synthesizing_Logic_with_Percolation_in_Nanoscale_Lattices.pdf | Synthesizing Logic with Percolation in Nanoscale Lattices]]
 
|- valign="top"
 
|- valign="top"
 
| '''authors''':
 
| '''authors''':
| Furkan Peker and [[Mustafa Altun]]
+
| [[Mustafa Altun]] and Marc Riedel
 
|- valign="top"
 
|- valign="top"
 
| '''appeared&nbsp;in''':
 
| '''appeared&nbsp;in''':
| width="624" | [http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=6687315 IEEE Transactions on Multi-Scale Computing Systems], Vol. 4, No. 4, pp. 522&ndash;532, 2018.
+
| [http://www.igi-global.com/Bookstore/TitleDetails.aspx?TitleId=1117&DetailsType=Description/ International Journal of Nanotechnology and Molecular Computation], Vol. 3, Issue 2, pp. 12&ndash;30, 2011.
 
|}
 
|}
 +
 
| align=center width="70" |  
 
| align=center width="70" |  
 
<span class="plainlinks">
 
<span class="plainlinks">
[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/7/71/Peker_Altun_Variation_Tolerant_Logic_Mapping_of_Nano_Crossbars.pdf]]</span>
+
[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/3/3b/Altun_Riedel_Synthesizing_Logic_with_Percolation_in_Nanoscale_Lattices.pdf]]</span>
 
<br>
 
<br>
[[Media:Peker_Altun_Variation_Tolerant_Logic_Mapping_of_Nano_Crossbars.pdf | Paper]]
+
[[Media:Altun_Riedel_Synthesizing_Logic_with_Percolation_in_Nanoscale_Lattices.pdf | Paper]]
 
|}
 
|}
  
 
{| style="border:2px solid #abd5f5; background:#f1f5fc;"
 
{| style="border:2px solid #abd5f5; background:#f1f5fc;"
 
 
|
 
|
{|
+
{|  
 
|- valign=top
 
|- valign=top
 
| width="100" |'''title''':
 
| width="100" |'''title''':
| width="550"|[[Media:Tunali_Altun_Nano_Crossbar_Yield_Analysis.pdf| Yield Analysis of Nano-Crossbar Arrays for Uniform and Clustered Defect Distributions]]
+
| width="550"|[[Media:Altun_Riedel_Lattice-Based_Computation_of_Boolean_Functions.pdf | Lattice Based Computation of Boolean Functions]]
 
|- valign="top"
 
|- valign="top"
 
| '''authors''':
 
| '''authors''':
| Onur Tunali and [[Mustafa Altun]]
+
| [[Mustafa Altun]] and Marc Riedel
 
|- valign="top"
 
|- valign="top"
 
| '''presented&nbsp;at''':
 
| '''presented&nbsp;at''':
| width="550"| [http://icecs2017.org/ IEEE International Conference on Electronics Circuits and Systems (ICECS)], Batumi, Georgia, 2017.
+
| [http://www.dac.com IEEE/ACM Design Automation Conference (DAC)], Anaheim, USA, 2010.
 
|}
 
|}
| align=center width="70" |
+
| align=center width="70" |  
 
<span class="plainlinks">
 
<span class="plainlinks">
[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/6/6b/Tunali_Altun_Nano_Crossbar_Yield_Analysis.pdf]]</span>
+
[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/7/7b/Altun_Riedel_Lattice-Based_Computation_of_Boolean_Functions.pdf]]</span>
 
<br>
 
<br>
[[Media:Tunali_Altun_Nano_Crossbar_Yield_Analysis.pdf | Paper]]
+
[[Media:Altun_Riedel_Lattice-Based_Computation_of_Boolean_Functions.pdf | Paper]]
| align="center" width="70" |
+
| align="center" width="70" |  
 
<span class="plainlinks">
 
<span class="plainlinks">
  
[[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/6/62/Tunali_Altun_Nano_Crossbar_Yield_Analysis.pptx]]
+
[[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/2/28/Altun_Riedel_Lattice-Based_Computation_of_Boolean_Functions.ppt]]
 
</span>
 
</span>
<br> [http://www.ecc.itu.edu.tr/images/6/62/Tunali_Altun_Nano_Crossbar_Yield_Analysis.pptx Slides]
+
<br> [http://www.ecc.itu.edu.tr/images/2/28/Altun_Riedel_Lattice-Based_Computation_of_Boolean_Functions.ppt Slides]
 
|}
 
|}
  
 
{| style="border:2px solid #abd5f5; background:#f1f5fc;"
 
{| style="border:2px solid #abd5f5; background:#f1f5fc;"
 +
 
|
 
|
 
{|  
 
{|  
 
|- valign=top
 
|- valign=top
 
| width="100" |'''title''':
 
| width="100" |'''title''':
| width="624"|[[Media:Tunali_Altun_Multiple_type_Defect_Tolerance_in_Nano_Crossbar_Arrays.pdf | A Fast Logic Mapping Algorithm for Multiple-type-Defect Tolerance in Reconfigurable Nano-Crossbar Arrays]]
+
| width="550"|[[Media:Altun_Riedel_Neuhauser_Nanoscale_Digital_Computation_Through_Percolation.pdf | Nanoscale Digital Computation Through Percolation]]
 
|- valign="top"
 
|- valign="top"
 
| '''authors''':
 
| '''authors''':
| Onur Tunali and [[Mustafa Altun]]
+
| [[Mustafa Altun]], Marc Riedel, and [http://www.cbs.umn.edu/eeb/contacts/claudia-neuhauser/ Claudia Neuhauser]
|- valign="top"
+
|- valign=top
| '''accepted&nbsp;in''':
+
| '''presented&nbsp;at''':
| width="624" | [http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=6245516 IEEE Transactions on Emerging Topics in Computing], DOI: 10.1109/TETC.2017.2755458, 2017.
+
| [http://www.dac.com IEEE/ACM Design Automation Conference (DAC)], San Francisco, USA, 2009.
 
|}
 
|}
 +
 
| align=center width="70" |  
 
| align=center width="70" |  
 
<span class="plainlinks">
 
<span class="plainlinks">
[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/c/c9/Tunali_Altun_Multiple_type_Defect_Tolerance_in_Nano_Crossbar_Arrays.pdf]]</span>
+
[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/0/0c/Altun_Riedel_Neuhauser_Nanoscale_Digital_Computation_Through_Percolation.pdf]]</span>
 
<br>
 
<br>
[[Media:Tunali_Altun_Multiple_type_Defect_Tolerance_in_Nano_Crossbar_Arrays.pdf | Paper]]
+
[[Media:Altun_Riedel_Neuhauser_Nanoscale_Digital_Computation_Through_Percolation.pdf | Paper]]
 +
| align="center" width="70" |
 +
<span class="plainlinks">
 +
 
 +
[[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/f/fe/Altun_Riedel_Neuhauser_Nanoscale_Digital_Computation_Through_Percolation.ppt]]
 +
</span>
 +
<br> [http://www.ecc.itu.edu.tr/images/f/fe/Altun_Riedel_Neuhauser_Nanoscale_Digital_Computation_Through_Percolation.ppt Slides]
 
|}
 
|}
 +
 +
== Energy Efficient ANN Hardware Implementation ==
  
 
{| style="border:2px solid #abd5f5; background:#f1f5fc;"
 
{| style="border:2px solid #abd5f5; background:#f1f5fc;"
Line 285: Line 279:
 
|- valign=top
 
|- valign=top
 
| width="100" |'''title''':
 
| width="100" |'''title''':
| width="624"|[[Media:Tunali_Altun_A_Survey_of_Nano-crossbar_Fault_Tolerance.pdf | A Survey of Fault Tolerance Algorithms for Reconfigurable Nano-Crossbar Arrays]]
+
| width="550"|[[Media:Aksoy_Parvin_Nojehdeh_Altun_Time_Multiplexed_ANN_Implementation.pdf | Efficient Time-Multiplexed Realization of Feedforward Artificial Neural Networks]]
 
|- valign="top"
 
|- valign="top"
 
| '''authors''':
 
| '''authors''':
| Onur Tunali and [[Mustafa Altun]]
+
| Levent Aksoy, Sajjad Parvin, Mohammadreza Nojehdeh, and [[Mustafa Altun]]
 
|- valign="top"
 
|- valign="top"
| '''appeared&nbsp;in''':
+
| '''presented&nbsp;at''':
| width="624" | [http://csur.acm.org/ ACM Computing Surveys], Vol. 50, No. 6, Article 79, 2017.  
+
| [http://iscas2020.org/ IEEE International Symposium on Circuits and Systems (ISCAS)], Seville, Spain, 2020.
 
|}
 
|}
 
| align=center width="70" |  
 
| align=center width="70" |  
 
<span class="plainlinks">
 
<span class="plainlinks">
[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/b/bc/Tunali_Altun_A_Survey_of_Nano-crossbar_Fault_Tolerance.pdf]]</span>
+
[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/e/eb/Aksoy_Parvin_Nojehdeh_Altun_Time_Multiplexed_ANN_Implementation.pdf]]</span>
 
<br>
 
<br>
[[Media:Tunali_Altun_A_Survey_of_Nano-crossbar_Fault_Tolerance.pdf | Paper]]
+
[[Media:Aksoy_Parvin_Nojehdeh_Altun_Time_Multiplexed_ANN_Implementation.pdf | Paper]]
 +
| align="center" width="70" |
 +
<span class="plainlinks">
 +
 
 +
[[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/3/3a/Aksoy_Parvin_Nojehdeh_Altun_Time_Multiplexed_ANN_Implementation.pptx]]
 +
</span>
 +
<br> [http://www.ecc.itu.edu.tr/images/3/3a/Aksoy_Parvin_Nojehdeh_Altun_Time_Multiplexed_ANN_Implementation.pptx Slides]
 
|}
 
|}
 +
 +
== Computing with Nano-Crossbar Arrays ==
 +
 +
=== Comprehensive Performance Optimization===
  
 
{| style="border:2px solid #abd5f5; background:#f1f5fc;"
 
{| style="border:2px solid #abd5f5; background:#f1f5fc;"
Line 305: Line 309:
 
|- valign=top
 
|- valign=top
 
| width="100" |'''title''':
 
| width="100" |'''title''':
| width="624"|[[Media:Tunali_Altun_Permanent_and_Transient_Fault_Tolerance_for_Reconfigurable_Nano-Crossbar_Arrays.pdf | Permanent and Transient Fault Tolerance for Reconfigurable Nano-Crossbar Arrays]]
+
| width="550"|[[Media:Altun_EtAl_NANOxCOMP_Lessons_Learned_Future_Directions.pdf | Nano-Crossbar based Computing: Lessons Learned and Future Directions]]
 
|- valign="top"
 
|- valign="top"
 
| '''authors''':
 
| '''authors''':
| Onur Tunali and [[Mustafa Altun]]
+
| [[Mustafa Altun]], Ismail Cevik, Ahmet Erten, Osman Eksik, Mircea Stan, and Csaba Andras Moritz
 
|- valign="top"
 
|- valign="top"
| '''appeared&nbsp;in''':
+
| '''presented&nbsp;at''':
| width="624" | [http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=43 IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems], Vol. 36, Issue 5, pp. 747&ndash;760, 2017.
+
| [http://www.date-conference.com/ Design, Automation, and Test in Europe (DATE)], Grenoble, France, 2020.
 
|}
 
|}
 
| align=center width="70" |  
 
| align=center width="70" |  
 
<span class="plainlinks">
 
<span class="plainlinks">
[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/c/cc/Tunali_Altun_Permanent_and_Transient_Fault_Tolerance_for_Reconfigurable_Nano-Crossbar_Arrays.pdf]]</span>
+
[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/0/04/Altun_EtAl_NANOxCOMP_Lessons_Learned_Future_Directions.pdf]]</span>
 
<br>
 
<br>
[[Media:Tunali_Altun_Permanent_and_Transient_Fault_Tolerance_for_Reconfigurable_Nano-Crossbar_Arrays.pdf | Paper]]
+
[[Media:Altun_EtAl_NANOxCOMP_Lessons_Learned_Future_Directions.pdf | Paper]]
 +
| align="center" width="70" |
 +
<span class="plainlinks">
 +
 
 +
[[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/9/9f/Altun_EtAl_NANOxCOMP_Lessons_Learned_Future_Directions.pptx]]
 +
</span>
 +
<br> [http://www.ecc.itu.edu.tr/images/9/9f/Altun_EtAl_NANOxCOMP_Lessons_Learned_Future_Directions.pptx Slides]
 
|}
 
|}
  
Line 325: Line 335:
 
|- valign=top
 
|- valign=top
 
| width="100" |'''title''':
 
| width="100" |'''title''':
| width="550"|[[Media:Tunali_Altun_Defect_Tolerance_in_Diode_FET_and_Four-Terminal_Switch_based_Nano-Crossbar_Arrays.pdf | Defect Tolerance in Diode FET and Four-Terminal Switch Based Nano-Crossbar Arrays]]
+
| width="550"|[[Media: Morgul_EtAl_Integrated_Synthesis_Methodology for_Crossbar_Arrays.pdf | Integrated Synthesis Methodology for Crossbar Arrays]]
 
|- valign="top"
 
|- valign="top"
 
| '''authors''':
 
| '''authors''':
| Onur Tunali and [[Mustafa Altun]]  
+
| width="550"| Ceylan Morgul, Luca Frontini, Onur Tunali, Ioana Vatajelu, Valentina Ciriani, Lorena Anghel, Csaba Moritz, Mircea Stan, Dan Alexandrescu, and [[Mustafa Altun]]  
 
|- valign="top"
 
|- valign="top"
 
| '''presented&nbsp;at''':
 
| '''presented&nbsp;at''':
| width="550"|[http://www.nanoarch.org/ IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH)], Boston, USA, 2015.
+
| width="550"|[http://www.nanoarch.org/ IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH)], Athens, Greece, 2018.
 
|}
 
|}
 
| align=center width="70" |  
 
| align=center width="70" |  
 
<span class="plainlinks">
 
<span class="plainlinks">
[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/e/ee/Tunali_Altun_Defect_Tolerance_in_Diode_FET_and_Four-Terminal_Switch_based_Nano-Crossbar_Arrays.pdf]]</span>
+
[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/b/b1/Morgul_EtAl_Integrated_Synthesis_Methodology_for_Crossbar_Arrays.pdf]]</span>
 
<br>
 
<br>
[[Media:Tunali_Altun_Defect_Tolerance_in_Diode_FET_and_Four-Terminal_Switch_based_Nano-Crossbar_Arrays.pdf | Paper]]
+
[[Media:Morgul_EtAl_Integrated_Synthesis_Methodology for_Crossbar_Arrays.pdf | Paper]]
 
| align="center" width="70" |  
 
| align="center" width="70" |  
 
<span class="plainlinks">
 
<span class="plainlinks">
  
[[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/f/f9/Tunali_Altun_Defect_Tolerance_in_Diode_FET_and_Four-Terminal_Switch_based_Nano-Crossbar_Arrays.pptx]]
+
[[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/b/bd/Morgul_EtAl_Integrated_Synthesis_Methodology_for_Crossbar_Arrays.pptx]]
 
</span>
 
</span>
<br> [http://www.ecc.itu.edu.tr/images/f/f9/Tunali_Altun_Defect_Tolerance_in_Diode_FET_and_Four-Terminal_Switch_based_Nano-Crossbar_Arrays.pptx Slides]
+
<br> [http://www.ecc.itu.edu.tr/images/b/bd/Morgul_EtAl_Integrated_Synthesis_Methodology_for_Crossbar_Arrays.pptx Slides]
 
|}
 
|}
  
 
{| style="border:2px solid #abd5f5; background:#f1f5fc;"
 
{| style="border:2px solid #abd5f5; background:#f1f5fc;"
 +
 
|
 
|
{|  
+
{|
 
|- valign=top
 
|- valign=top
 
| width="100" |'''title''':
 
| width="100" |'''title''':
| width="624"|[[Media:Altun_Riedel_Synthesizing_Logic_with_Percolation_in_Nanoscale_Lattices.pdf | Synthesizing Logic with Percolation in Nanoscale Lattices]]
+
| width="550"|[[Media:Tunali_Altun_Logic_Synthesis_and_Defect_Tolerance_for_Memristive_Crossbars.pdf| Logic Synthesis and Defect Tolerance for Memristive Crossbar Arrays]]
 
|- valign="top"
 
|- valign="top"
 
| '''authors''':
 
| '''authors''':
| [[Mustafa Altun]] and Marc Riedel
+
| Onur Tunali and [[Mustafa Altun]]
 
|- valign="top"
 
|- valign="top"
| '''appeared&nbsp;in''':
+
| '''presented&nbsp;at''':
| [http://www.igi-global.com/Bookstore/TitleDetails.aspx?TitleId=1117&DetailsType=Description/ International Journal of Nanotechnology and Molecular Computation], Vol. 3, Issue 2, pp. 12&ndash;30, 2011.
+
| width="550"| [http://www.date-conference.com/ Design, Automation and Test in Europe (DATE)], Dresden, Germany, 2018.
 
|}
 
|}
 
+
| align=center width="70" |
| align=center width="70" |  
+
 
<span class="plainlinks">
 
<span class="plainlinks">
[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/3/3b/Altun_Riedel_Synthesizing_Logic_with_Percolation_in_Nanoscale_Lattices.pdf]]</span>
+
[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/5/57/Tunali_Altun_Logic_Synthesis_and_Defect_Tolerance_for_Memristive_Crossbars.pdf]]</span>
 
<br>
 
<br>
[[Media:Altun_Riedel_Synthesizing_Logic_with_Percolation_in_Nanoscale_Lattices.pdf | Paper]]
+
[[Media:Tunali_Altun_Logic_Synthesis_and_Defect_Tolerance_for_Memristive_Crossbars.pdf | Paper]]
 +
| align="center" width="70" |
 +
<span class="plainlinks">
 +
 
 +
[[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/b/b8/Tunali_Altun_Logic_Synthesis_and_Defect_Tolerance_for_Memristive_Crossbars.pptx]]
 +
</span>
 +
<br> [http://www.ecc.itu.edu.tr/images/b/b8/Tunali_Altun_Logic_Synthesis_and_Defect_Tolerance_for_Memristive_Crossbars.pptx Slides]
 
|}
 
|}
  
Line 373: Line 389:
 
|- valign=top
 
|- valign=top
 
| width="100" |'''title''':
 
| width="100" |'''title''':
| width="550"|[[Media:Altun_Riedel_Neuhauser_Nanoscale_Digital_Computation_Through_Percolation.pdf | Nanoscale Digital Computation Through Percolation]]
+
| width="550"|[[Media:Altun_EtAl_Synthesis_and_Testing_for_Switching_Nano_Crossbar_Arrays.pdf | Logic Synthesis and Testing Techniques for Switching Nano-Crossbar Arrays]]
 
|- valign="top"
 
|- valign="top"
 
| '''authors''':
 
| '''authors''':
| [[Mustafa Altun]], Marc Riedel, and [http://www.cbs.umn.edu/eeb/contacts/claudia-neuhauser/ Claudia Neuhauser]
+
| width="550"| Dan Alexandrescu, [[Mustafa Altun]], Lorena Anghel, Anna Bernasconi, Valentina Ciriani, Luca Frontini, and Mehdi Tahoori
 
|- valign=top
 
|- valign=top
| '''presented&nbsp;at''':
+
| '''appeared&nbsp;in''':
| [http://www.dac.com IEEE/ACM Design Automation Conference (DAC)], San Francisco, USA, 2009.
+
| width="624" | [http://www.journals.elsevier.com/microprocessors-and-microsystems/ Microprocessors and Microsystems], Vol. 54, pp. 14&ndash;25, 2017.
 
|}
 
|}
 
 
| align=center width="70" |  
 
| align=center width="70" |  
 
<span class="plainlinks">
 
<span class="plainlinks">
[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/0/0c/Altun_Riedel_Neuhauser_Nanoscale_Digital_Computation_Through_Percolation.pdf]]</span>
+
[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/0/0a/Altun_EtAl_Synthesis_and_Testing_for_Switching_Nano_Crossbar_Arrays.pdf]]</span>
 
<br>
 
<br>
[[Media:Altun_Riedel_Neuhauser_Nanoscale_Digital_Computation_Through_Percolation.pdf | Paper]]
+
[[Media:Altun_EtAl_Synthesis_and_Testing_for_Switching_Nano_Crossbar_Arrays.pdf | Paper]]
| align="center" width="70" |
+
<span class="plainlinks">
+
  
[[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/f/fe/Altun_Riedel_Neuhauser_Nanoscale_Digital_Computation_Through_Percolation.ppt]]
 
</span>
 
<br> [http://www.ecc.itu.edu.tr/images/f/fe/Altun_Riedel_Neuhauser_Nanoscale_Digital_Computation_Through_Percolation.ppt Slides]
 
 
|}
 
|}
 
=== Logic Synthesis ===
 
  
 
{| style="border:2px solid #abd5f5; background:#f1f5fc;"
 
{| style="border:2px solid #abd5f5; background:#f1f5fc;"
 
 
|
 
|
{|
+
{|  
 
|- valign=top
 
|- valign=top
 
| width="100" |'''title''':
 
| width="100" |'''title''':
| width="550"|[[Media: Aksoy_Altun_SAT_based_Synthesis_of_Switching_Lattices.pdf| A Satisfiability-Based Approximate Algorithm for Logic Synthesis Using Switching Lattices]]
+
| width="550"|[[Media:Altun_Ciriani_Tahoori_Computing_with_Nano-Crossbar_Arrays.pdf | Computing with Nano-Crossbar Arrays: Logic Synthesis and Fault Tolerance]]
 
|- valign="top"
 
|- valign="top"
 
| '''authors''':
 
| '''authors''':
| Levent Aksoy and [[Mustafa Altun]]
+
| [[Mustafa Altun]], Valentina Ciriani, and Mehdi Tahoori
 
|- valign="top"
 
|- valign="top"
 
| '''presented&nbsp;at''':
 
| '''presented&nbsp;at''':
| width="550"| [http://www.date-conference.com/ Design, Automation and Test in Europe (DATE)], Florence, Italy, 2019.
+
| [http://www.date-conference.com/ Design, Automation and Test in Europe (DATE)], Lausanne, Switzerland, 2017.
 
|}
 
|}
| align=center width="70" |
+
| align=center width="70" |  
 
<span class="plainlinks">
 
<span class="plainlinks">
[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/f/fe/Aksoy_Altun_SAT_based_Synthesis_of_Switching_Lattices.pdf]]</span>
+
[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/0/09/Altun_Ciriani_Tahoori_Computing_with_Nano-Crossbar_Arrays.pdf]]</span>
 
<br>
 
<br>
[[Media:Aksoy_Altun_SAT_based_Synthesis_of_Switching_Lattices.pdf | Paper]]
+
[[Media:Altun_Ciriani_Tahoori_Computing_with_Nano-Crossbar_Arrays.pdf | Paper]]
| align="center" width="70" |
+
| align="center" width="70" |  
 
<span class="plainlinks">
 
<span class="plainlinks">
  
[[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/5/54/Aksoy_Altun_SAT_based_Synthesis_of_Switching_Lattices.pptx]]
+
[[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/2/28/Altun_Ciriani_Tahoori_Computing_with_Nano-Crossbar_Arrays.pptx]]
 
</span>
 
</span>
<br> [http://www.ecc.itu.edu.tr/images/5/54/Aksoy_Altun_SAT_based_Synthesis_of_Switching_Lattices.pptx Slides]
+
<br> [http://www.ecc.itu.edu.tr/images/2/28/Altun_Ciriani_Tahoori_Computing_with_Nano-Crossbar_Arrays.pptx Slides]
 
|}
 
|}
  
 
{| style="border:2px solid #abd5f5; background:#f1f5fc;"
 
{| style="border:2px solid #abd5f5; background:#f1f5fc;"
 +
 
|
 
|
 
{|  
 
{|  
 
|- valign=top
 
|- valign=top
 
| width="100" |'''title''':
 
| width="100" |'''title''':
| width="624"|[[Media:Morgul_Altun_Algorithms_for_Switching_Lattices.pdf | Optimal and Heuristic Algorithms to Synthesize Lattices of Four-Terminal Switches]]
+
| width="550"|[[Media:Altun_EtAl_Synthesis_and_Performance_Optimization_of_a_Switching_Nano-crossbar_Computer.pdf | Synthesis and Performance Optimization of a Switching Nano-crossbar Computer]]
 
|- valign="top"
 
|- valign="top"
 
| '''authors''':
 
| '''authors''':
| Ceylan Morgul and [[Mustafa Altun]]
+
| width="550"| Dan Alexandrescu, [[Mustafa Altun]], Lorena Anghel, Anna Bernasconi, Valentina Ciriani, and Mehdi Tahoori
|- valign="top"
+
|- valign=top
| '''appeared&nbsp;in''':
+
| '''presented&nbsp;at''':
| width="624" | [http://www.journals.elsevier.com/integration Integration, the VLSI Journal], Vol. 64, pp. 60&ndash;70, 2019.
+
| [http://dsd-seaa2016.cs.ucy.ac.cy/index.php Euromicro Conference on Digital System Design (DSD)], Limassol, Cyprus, 2016.
 
|}
 
|}
 +
 
| align=center width="70" |  
 
| align=center width="70" |  
 
<span class="plainlinks">
 
<span class="plainlinks">
[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/5/58/Morgul_Altun_Algorithms_for_Switching_Lattices.pdf]]</span>
+
[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/a/ab/Altun_EtAl_Synthesis_and_Performance_Optimization_of_a_Switching_Nano-crossbar_Computer.pdf]]</span>
 
<br>
 
<br>
[[Media:Morgul_Altun_Algorithms_for_Switching_Lattices.pdf | Paper]]
+
[[Media:Altun_EtAl_Synthesis_and_Performance_Optimization_of_a_Switching_Nano-crossbar_Computer.pdf | Paper]]
 +
| align="center" width="70" |
 +
<span class="plainlinks">
 +
 
 +
[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/7/7f/Altun_EtAl_Synthesis_and_Performance_Optimization_of_a_Switching_Nano-crossbar_Computer_SLIDES.pdf]]
 +
</span>
 +
<br> [[Media:Altun_EtAl_Synthesis_and_Performance_Optimization_of_a_Switching_Nano-crossbar_Computer_SLIDES.pdf | Slides]]
 
|}
 
|}
  
Line 450: Line 465:
 
|- valign=top
 
|- valign=top
 
| width="100" |'''title''':
 
| width="100" |'''title''':
| width="550"|[[Media:Morgul_Altun_Synthesis_and_Optimization_of_Switching_Nanoarrays.pdf | Synthesis and Optimization of Switching Nanoarrays]]
+
| width="550"|[[Media:Morgul_Peker_Altun_Power-Delay-Area_Performance_Modeling_and_Analysis_for_Nano-Crossbar_Arrays.pdf | Power-Delay-Area Performance Modeling and Analysis for Nano-Crossbar Arrays]]
 
|- valign="top"
 
|- valign="top"
 
| '''authors''':
 
| '''authors''':
| Ceylan Morgul and [[Mustafa Altun]]
+
| Ceylan Morgul, Furkan Peker, and [[Mustafa Altun]]
 
|- valign=top
 
|- valign=top
 
| '''presented&nbsp;at''':
 
| '''presented&nbsp;at''':
| width="550"| [http://www.ddecs2015.org/ IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS)], Belgrade, Serbia, 2015.
+
| [http://www.eng.ucy.ac.cy/theocharides/isvlsi16/ IEEE Computer Society Annual Symposium on VLSI (ISVLSI)], Pittsburgh, USA, 2016.
 
|}
 
|}
  
 
| align=center width="70" |  
 
| align=center width="70" |  
 
<span class="plainlinks">
 
<span class="plainlinks">
[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/5/59/Morgul_Altun_Synthesis_and_Optimization_of_Switching_Nanoarrays.pdf]]</span>
+
[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/8/8f/Morgul_Peker_Altun_Power-Delay-Area_Performance_Modeling_and_Analysis_for_Nano-Crossbar_Arrays.pdf]]</span>
 
<br>
 
<br>
[[Media:Morgul_Altun_Synthesis_and_Optimization_of_Switching_Nanoarrays.pdf | Paper]]
+
[[Media:Morgul_Peker_Altun_Power-Delay-Area_Performance_Modeling_and_Analysis_for_Nano-Crossbar_Arrays.pdf | Paper]]
 
| align="center" width="70" |  
 
| align="center" width="70" |  
 
<span class="plainlinks">
 
<span class="plainlinks">
  
[[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/1/1a/Morgul_Altun_Synthesis_and_Optimization_of_Switching_Nanoarrays.pptx]]
+
[[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/5/5a/Morgul_Peker_Altun_Power-Delay-Area_Performance_Modeling_and_Analysis_for_Nano-Crossbar_Arrays.pptx]]
 
</span>
 
</span>
<br> [http://www.ecc.itu.edu.tr/images/1/1a/Morgul_Altun_Synthesis_and_Optimization_of_Switching_Nanoarrays.pptx Slides]
+
<br> [http://www.ecc.itu.edu.tr/images/5/5a/Morgul_Peker_Altun_Power-Delay-Area_Performance_Modeling_and_Analysis_for_Nano-Crossbar_Arrays.pptx Poster]
 
|}
 
|}
 +
 +
=== Logic Synthesis and Fault/Variation Tolerance ===
  
 
{| style="border:2px solid #abd5f5; background:#f1f5fc;"
 
{| style="border:2px solid #abd5f5; background:#f1f5fc;"
Line 477: Line 494:
 
|- valign=top
 
|- valign=top
 
| width="100" |'''title''':
 
| width="100" |'''title''':
| width="624"|[[Media:Altun_Riedel_Logic_Synthesis_for_Switching_Lattices.pdf | Logic Synthesis for Switching Lattices]]
+
| width="624"|[[Media:Tunali_Altun_Multiple_type_Defect_Tolerance_in_Nano_Crossbar_Arrays.pdf | A Fast Logic Mapping Algorithm for Multiple-type-Defect Tolerance in Reconfigurable Nano-Crossbar Arrays]]
 
|- valign="top"
 
|- valign="top"
 
| '''authors''':
 
| '''authors''':
| [[Mustafa Altun]] and Marc Riedel
+
| Onur Tunali and [[Mustafa Altun]]
 
|- valign="top"
 
|- valign="top"
 
| '''appeared&nbsp;in''':
 
| '''appeared&nbsp;in''':
| [http://www.computer.org/portal/web/tc IEEE Transactions on Computers], Vol. 61, Issue 11, pp. 1588&ndash;1600, 2012.
+
| width="624" | [http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=6245516 IEEE Transactions on Emerging Topics in Computing], Vol. 7, Issue 4, pp. 518&ndash;529, 2019.
<!-- |- valign="top"
+
| '''presented&nbsp;at''':
+
| width="624"| [http://fias.uni-frankfurt.de International Conference on Computational Modelling of Nanostructured Materials (ICCMNM)-FIAS], Frankfurt, Germany, 2013. -->
+
 
|}
 
|}
 
| align=center width="70" |  
 
| align=center width="70" |  
 
<span class="plainlinks">
 
<span class="plainlinks">
[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/c/ca/Altun_Riedel_Logic_Synthesis_for_Switching_Lattices.pdf]]</span>
+
[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/c/c9/Tunali_Altun_Multiple_type_Defect_Tolerance_in_Nano_Crossbar_Arrays.pdf]]</span>
 
<br>
 
<br>
[[Media:Altun_Riedel_Logic_Synthesis_for_Switching_Lattices.pdf | Paper]]
+
[[Media:Tunali_Altun_Multiple_type_Defect_Tolerance_in_Nano_Crossbar_Arrays.pdf | Paper]]
 
|}
 
|}
  
Line 500: Line 514:
 
|- valign=top
 
|- valign=top
 
| width="100" |'''title''':
 
| width="100" |'''title''':
| width="550"|[[Media:Altun_Riedel_Lattice-Based_Computation_of_Boolean_Functions.pdf | Lattice Based Computation of Boolean Functions]]
+
| width="624"|[[Media:Tunali_Morgul_Altun_Defect_Tolerant_Memristor_Crossbars.pdf | Defect Tolerant Logic Synthesis for Memristor Crossbars with Performance Evaluation]]
 
|- valign="top"
 
|- valign="top"
 
| '''authors''':
 
| '''authors''':
| [[Mustafa Altun]] and Marc Riedel
+
| Onur Tunali, Ceylan Morgul, and [[Mustafa Altun]]
 
|- valign="top"
 
|- valign="top"
| '''presented&nbsp;at''':
+
| '''appeared&nbsp;in''':
| [http://www.dac.com IEEE/ACM Design Automation Conference (DAC)], Anaheim, USA, 2010.
+
| width="624" | [http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=40 IEEE Micro], Vol. 38, Issue 5, pp. 22&ndash;31, 2018.
 
|}
 
|}
 
| align=center width="70" |  
 
| align=center width="70" |  
 
<span class="plainlinks">
 
<span class="plainlinks">
[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/7/7b/Altun_Riedel_Lattice-Based_Computation_of_Boolean_Functions.pdf]]</span>
+
[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/d/db/Tunali_Morgul_Altun_Defect_Tolerant_Memristor_Crossbars.pdf]]</span>
 
<br>
 
<br>
[[Media:Altun_Riedel_Lattice-Based_Computation_of_Boolean_Functions.pdf | Paper]]
+
[[Media:Tunali_Morgul_Altun_Defect_Tolerant_Memristor_Crossbars.pdf | Paper]]
| align="center" width="70" |
+
<span class="plainlinks">
+
 
+
[[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/2/28/Altun_Riedel_Lattice-Based_Computation_of_Boolean_Functions.ppt]]
+
</span>
+
<br> [http://www.ecc.itu.edu.tr/images/2/28/Altun_Riedel_Lattice-Based_Computation_of_Boolean_Functions.ppt Slides]
+
 
|}
 
|}
 
==== National Publications in Turkish ====
 
  
 
{| style="border:2px solid #abd5f5; background:#f1f5fc;"
 
{| style="border:2px solid #abd5f5; background:#f1f5fc;"
 
 
|
 
|
 
{|  
 
{|  
 
|- valign=top
 
|- valign=top
 
| width="100" |'''title''':
 
| width="100" |'''title''':
| width="550"|[[Media:Morgul_Altun_Anahtarlamali_Nano_Dizinler_ile_Lojik_Devre_Tasarimi_ve_Boyut_Optimizasyonu.pdf | Logic Circuit Design with Switching Nano Arrays and Area Optimization]]
+
| width="624"|[[Media:Peker_Altun_Variation_Tolerant_Logic_Mapping_of_Nano_Crossbars.pdf | A Fast Hill Climbing Algorithm for Defect and Variation Tolerant Logic Mapping of Nano-Crossbar Arrays]]
|- valign="top
+
|- valign="top"
| width="100" |'''title (in Turkish)''':
+
| width="550"|[[Media:Morgul_Altun_Anahtarlamali_Nano_Dizinler_ile_Lojik_Devre_Tasarimi_ve_Boyut_Optimizasyonu.pdf | Anahtarlamalı Nano Dizinler ile Lojik Devre Tasarımı ve Boyut Optimizasyonu]]
+
|- valign="top
+
 
| '''authors''':
 
| '''authors''':
| Ceylan Morgul and [[Mustafa Altun]]
+
| Furkan Peker and [[Mustafa Altun]]
 
|- valign="top"
 
|- valign="top"
| '''presented at''':
+
| '''appeared&nbsp;in''':
| width="550"| [http://www.eleco.org.tr/ Elektrik, Elektronik, Bilgisayar ve Biyomedikal Mühendisliği Sempozyumu (ELECO)], Bursa, Turkey, 2014.
+
| width="624" | [http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=6687315 IEEE Transactions on Multi-Scale Computing Systems], Vol. 4, No. 4, pp. 522&ndash;532, 2018.
 
|}
 
|}
 
 
| align=center width="70" |  
 
| align=center width="70" |  
 
<span class="plainlinks">
 
<span class="plainlinks">
 
+
[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/7/71/Peker_Altun_Variation_Tolerant_Logic_Mapping_of_Nano_Crossbars.pdf]]</span>
[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/9/99/Morgul_Altun_Anahtarlamali_Nano_Dizinler_ile_Lojik_Devre_Tasarimi_ve_Boyut_Optimizasyonu.pdf]]</span>
+
 
<br>
 
<br>
[[Media:Morgul_Altun_Anahtarlamali_Nano_Dizinler_ile_Lojik_Devre_Tasarimi_ve_Boyut_Optimizasyonu.pdf | Paper]]
+
[[Media:Peker_Altun_Variation_Tolerant_Logic_Mapping_of_Nano_Crossbars.pdf | Paper]]
 
+
| align="center" width="70" |
+
<span class="plainlinks">
+
 
+
[[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/a/aa/Morgul_Altun_Anahtarlamali_Nano_Dizinler_ile_Lojik_Devre_Tasarimi_ve_Boyut_Optimizasyonu.pptx]]
+
</span>
+
<br> [http://www.ecc.itu.edu.tr/images/a/aa/Morgul_Altun_Anahtarlamali_Nano_Dizinler_ile_Lojik_Devre_Tasarimi_ve_Boyut_Optimizasyonu.pptx Slides]
+
 
|}
 
|}
 
== Reversible Computing ==
 
 
=== CMOS Fault Tolerance ===
 
  
 
{| style="border:2px solid #abd5f5; background:#f1f5fc;"
 
{| style="border:2px solid #abd5f5; background:#f1f5fc;"
  
 
|
 
|
{|  
+
{|
 
|- valign=top
 
|- valign=top
 
| width="100" |'''title''':
 
| width="100" |'''title''':
| width="550"|[[Media:Parvin_Altun_CMOS_Fault_Tolerance_with_Preservative_Reversible_Gates.pdf | Implementation of CMOS Logic Circuits with Perfect Fault Detection Using Preservative Reversible Gates]]
+
| width="550"|[[Media:Tunali_Altun_Nano_Crossbar_Yield_Analysis.pdf| Yield Analysis of Nano-Crossbar Arrays for Uniform and Clustered Defect Distributions]]
 
|- valign="top"
 
|- valign="top"
 
| '''authors''':
 
| '''authors''':
| Sajjad Parvin and [[Mustafa Altun]]
+
| Onur Tunali and [[Mustafa Altun]]
|- valign=top
+
|- valign="top"
 
| '''presented&nbsp;at''':
 
| '''presented&nbsp;at''':
| width="550"| [http://tima.univ-grenoble-alpes.fr/conferences/iolts/iolts19/ IEEE International Symposium on On-Line Testing and Robust System Design (IOLTS)], Rhodes Island, Greece, 2019.
+
| width="550"| [http://icecs2017.org/ IEEE International Conference on Electronics Circuits and Systems (ICECS)], Batumi, Georgia, 2017.
 
|}
 
|}
 
+
| align=center width="70" |
| align=center width="70" |  
+
 
<span class="plainlinks">
 
<span class="plainlinks">
[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/e/ee/Parvin_Altun_CMOS_Fault_Tolerance_with_Preservative_Reversible_Gates.pdf]]</span>
+
[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/6/6b/Tunali_Altun_Nano_Crossbar_Yield_Analysis.pdf]]</span>
 
<br>
 
<br>
[[Media:Parvin_Altun_CMOS_Fault_Tolerance_with_Preservative_Reversible_Gates.pdf | Paper]]
+
[[Media:Tunali_Altun_Nano_Crossbar_Yield_Analysis.pdf | Paper]]
| align="center" width="70" |  
+
| align="center" width="70" |
 
<span class="plainlinks">
 
<span class="plainlinks">
  
[[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/f/f4/Parvin_Altun_CMOS_Fault_Tolerance_with_Preservative_Reversible_Gates.pptx]]
+
[[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/6/62/Tunali_Altun_Nano_Crossbar_Yield_Analysis.pptx]]
 
</span>
 
</span>
<br> [http://www.ecc.itu.edu.tr/images/f/f4/Parvin_Altun_CMOS_Fault_Tolerance_with_Preservative_Reversible_Gates.pptx Poster]
+
<br> [http://www.ecc.itu.edu.tr/images/6/62/Tunali_Altun_Nano_Crossbar_Yield_Analysis.pptx Slides]
 
|}
 
|}
  
{| style="border:2px solid #abd5f5; background:#f1f5fc; "
+
{| style="border:2px solid #abd5f5; background:#f1f5fc;"
 
+
 
|
 
|
{|
+
{|  
 
|- valign=top
 
|- valign=top
 
| width="100" |'''title''':
 
| width="100" |'''title''':
| width="624"|[[Media:Altun_Parvin_Cilasun_Exploiting_Reversible_Computing_for_CMOS_Fault_Tolerance.pdf| Exploiting Reversible Computing for Latent-Fault-Free Error Detecting/Correcting CMOS Circuits
+
| width="624"|[[Media:Tunali_Altun_A_Survey_of_Nano-crossbar_Fault_Tolerance.pdf | A Survey of Fault Tolerance Algorithms for Reconfigurable Nano-Crossbar Arrays]]
]]
+
 
|- valign="top"
 
|- valign="top"
 
| '''authors''':
 
| '''authors''':
| [[Mustafa Altun]], Sajjad Parvin, and Husrev Cilasun
+
| Onur Tunali and [[Mustafa Altun]]
 
|- valign="top"
 
|- valign="top"
 
| '''appeared&nbsp;in''':
 
| '''appeared&nbsp;in''':
| [http://ieeeaccess.ieee.org/ IEEE Access], Vol. 6, pp. 74475&ndash;74484, 2018.
+
| width="624" | [http://csur.acm.org/ ACM Computing Surveys], Vol. 50, No. 6,  Article 79, 2017.  
 
|}
 
|}
| align=center width="70" |
+
| align=center width="70" |  
 
<span class="plainlinks">
 
<span class="plainlinks">
[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/7/7d/Altun_Parvin_Cilasun_Exploiting_Reversible_Computing_for_CMOS_Fault_Tolerance.pdf]]</span>
+
[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/b/bc/Tunali_Altun_A_Survey_of_Nano-crossbar_Fault_Tolerance.pdf]]</span>
 
<br>
 
<br>
[[Media:Altun_Parvin_Cilasun_Exploiting_Reversible_Computing_for_CMOS_Fault_Tolerance.pdf | Paper]]
+
[[Media:Tunali_Altun_A_Survey_of_Nano-crossbar_Fault_Tolerance.pdf | Paper]]
 
+
 
|}
 
|}
  
{| style="border:2px solid #abd5f5; background:#f1f5fc; "
+
{| style="border:2px solid #abd5f5; background:#f1f5fc;"
 
+
 
|
 
|
{|
+
{|  
 
|- valign=top
 
|- valign=top
 
| width="100" |'''title''':
 
| width="100" |'''title''':
| width="624"|[[Media:Cilasun_Altun_A_Novel_Reversible_Fault_Tolerant_Microprocessor.pdf| A Novel Reversible Fault Tolerant Microprocessor Design in AMS 0.35um Process
+
| width="624"|[[Media:Tunali_Altun_Permanent_and_Transient_Fault_Tolerance_for_Reconfigurable_Nano-Crossbar_Arrays.pdf | Permanent and Transient Fault Tolerance for Reconfigurable Nano-Crossbar Arrays]]
]]
+
 
|- valign="top"
 
|- valign="top"
 
| '''authors''':
 
| '''authors''':
| Husrev Cilasun and [[Mustafa Altun]]
+
| Onur Tunali and [[Mustafa Altun]]
 
|- valign="top"
 
|- valign="top"
 
| '''appeared&nbsp;in''':
 
| '''appeared&nbsp;in''':
| [http://www.journals.istanbul.edu.tr/iujeee/index Istanbul University - Journal of Electrical & Electronics Engineering], Vol. 17, No. 1, pp. 3147&ndash;3154, 2017.
+
| width="624" | [http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=43 IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems], Vol. 36, Issue 5, pp. 747&ndash;760, 2017.
 
|}
 
|}
| align=center width="70" |
+
| align=center width="70" |  
 
<span class="plainlinks">
 
<span class="plainlinks">
[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/3/30/Cilasun_Altun_A_Novel_Reversible_Fault_Tolerant_Microprocessor.pdf]]</span>
+
[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/c/cc/Tunali_Altun_Permanent_and_Transient_Fault_Tolerance_for_Reconfigurable_Nano-Crossbar_Arrays.pdf]]</span>
 
<br>
 
<br>
[[Media:Cilasun_Altun_A_Novel_Reversible_Fault_Tolerant_Microprocessor.pdf | Paper]]
+
[[Media:Tunali_Altun_Permanent_and_Transient_Fault_Tolerance_for_Reconfigurable_Nano-Crossbar_Arrays.pdf | Paper]]
 
+
 
|}
 
|}
  
=== Logic Synthesis ===
+
{| style="border:2px solid #abd5f5; background:#f1f5fc;"
 
+
{| style="border:2px solid #abd5f5; background:#f1f5fc; "
+
 
+
 
|
 
|
{|
+
{|  
 
|- valign=top
 
|- valign=top
 
| width="100" |'''title''':
 
| width="100" |'''title''':
| width="624"|[[Media:Susam_Altun_Fast_Synthesis_of_Reversible_Circuits_using_a_Sorting_Algorithm_and_Optimization.pdf| Fast Synthesis of Reversible Circuits using a Sorting Algorithm and Optimization]]
+
| width="550"|[[Media:Tunali_Altun_Defect_Tolerance_in_Diode_FET_and_Four-Terminal_Switch_based_Nano-Crossbar_Arrays.pdf | Defect Tolerance in Diode FET and Four-Terminal Switch Based Nano-Crossbar Arrays]]
 
|- valign="top"
 
|- valign="top"
 
| '''authors''':
 
| '''authors''':
| Omercan Susam and [[Mustafa Altun]]
+
| Onur Tunali and [[Mustafa Altun]]  
 
|- valign="top"
 
|- valign="top"
| '''appeared&nbsp;in''':
+
| '''presented&nbsp;at''':
| [http://www.oldcitypublishing.com/journals/mvlsc-home/ Journal of Multiple-Valued Logic and Soft Computing], Vol. 29, Issue 1-2, pp. 1&ndash;23, 2017.
+
| width="550"|[http://www.nanoarch.org/ IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH)], Boston, USA, 2015.
 
|}
 
|}
| align=center width="70" |
+
| align=center width="70" |  
 
<span class="plainlinks">
 
<span class="plainlinks">
[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/c/cd/Susam_Altun_Fast_Synthesis_of_Reversible_Circuits_using_a_Sorting_Algorithm_and_Optimization.pdf]]</span>
+
[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/e/ee/Tunali_Altun_Defect_Tolerance_in_Diode_FET_and_Four-Terminal_Switch_based_Nano-Crossbar_Arrays.pdf]]</span>
 
<br>
 
<br>
[[Media:Susam_Altun_Fast_Synthesis_of_Reversible_Circuits_using_a_Sorting_Algorithm_and_Optimization.pdf | Paper]]
+
[[Media:Tunali_Altun_Defect_Tolerance_in_Diode_FET_and_Four-Terminal_Switch_based_Nano-Crossbar_Arrays.pdf | Paper]]
 +
| align="center" width="70" |
 +
<span class="plainlinks">
  
 +
[[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/f/f9/Tunali_Altun_Defect_Tolerance_in_Diode_FET_and_Four-Terminal_Switch_based_Nano-Crossbar_Arrays.pptx]]
 +
</span>
 +
<br> [http://www.ecc.itu.edu.tr/images/f/f9/Tunali_Altun_Defect_Tolerance_in_Diode_FET_and_Four-Terminal_Switch_based_Nano-Crossbar_Arrays.pptx Slides]
 
|}
 
|}
  
Line 661: Line 645:
  
 
|
 
|
{|
+
{|  
 
|- valign=top
 
|- valign=top
 
| width="100" |'''title''':
 
| width="100" |'''title''':
| width="550"|[[Media:Susam_Altun_An_Efficient_Algorithm_to_Synthesize_Quantum_Circuits_and_Optimization.pdf| An Efficient Algorithm to Synthesize Quantum Circuits and Optimization]]
+
| width="550"|[[Media:Morgul_Altun_Synthesis_and_Optimization_of_Switching_Nanoarrays.pdf | Synthesis and Optimization of Switching Nanoarrays]]
 
|- valign="top"
 
|- valign="top"
 
| '''authors''':
 
| '''authors''':
| Omercan Susam and [[Mustafa Altun]]
+
| Ceylan Morgul and [[Mustafa Altun]]
|- valign="top"
+
|- valign=top
 
| '''presented&nbsp;at''':
 
| '''presented&nbsp;at''':
| width="550"| [http://www.ieee-icecs2014.org/ IEEE International Conference on Electronics Circuits and Systems (ICECS)], Marseille, France, 2014.
+
| width="550"| [http://www.ddecs2015.org/ IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS)], Belgrade, Serbia, 2015.
 
|}
 
|}
| align=center width="70" |
+
 
 +
| align=center width="70" |  
 
<span class="plainlinks">
 
<span class="plainlinks">
[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/7/71/Susam_Altun_An_Efficient_Algorithm_to_Synthesize_Quantum_Circuits_and_Optimization.pdf]]</span>
+
[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/5/59/Morgul_Altun_Synthesis_and_Optimization_of_Switching_Nanoarrays.pdf]]</span>
 
<br>
 
<br>
[[Media:Susam_Altun_An_Efficient_Algorithm_to_Synthesize_Quantum_Circuits_and_Optimization.pdf | Paper]]
+
[[Media:Morgul_Altun_Synthesis_and_Optimization_of_Switching_Nanoarrays.pdf | Paper]]
| align="center" width="70" |
+
| align="center" width="70" |  
 
<span class="plainlinks">
 
<span class="plainlinks">
  
[[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/d/d0/Susam_Altun_An_Efficient_Algorithm_to_Synthesize_Quantum_Circuits_and_Optimization.pptx]]
+
[[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/1/1a/Morgul_Altun_Synthesis_and_Optimization_of_Switching_Nanoarrays.pptx]]
 
</span>
 
</span>
<br> [http://www.ecc.itu.edu.tr/images/d/d0/Susam_Altun_An_Efficient_Algorithm_to_Synthesize_Quantum_Circuits_and_Optimization.pptx Slides]
+
<br> [http://www.ecc.itu.edu.tr/images/1/1a/Morgul_Altun_Synthesis_and_Optimization_of_Switching_Nanoarrays.pptx Slides]
 
|}
 
|}
  
Line 693: Line 678:
 
|- valign=top
 
|- valign=top
 
| width="100" |'''title''':
 
| width="100" |'''title''':
| width="550"|[[Media:Susam_Altun_Kuantum_Devre_Sentezi_ve_Optimizasyonu_icin_Verimli_Bir_Algoritma.pdf | Kuantum Devre Sentezi ve Optimizasyonu için Verimli bir Algoritma]]
+
| width="550"|[[Media:Morgul_Altun_Anahtarlamali_Nano_Dizinler_ile_Lojik_Devre_Tasarimi_ve_Boyut_Optimizasyonu.pdf | Logic Circuit Design with Switching Nano Arrays and Area Optimization]]
 +
|- valign="top
 +
| width="100" |'''title (in Turkish)''':
 +
| width="550"|[[Media:Morgul_Altun_Anahtarlamali_Nano_Dizinler_ile_Lojik_Devre_Tasarimi_ve_Boyut_Optimizasyonu.pdf | Anahtarlamalı Nano Dizinler ile Lojik Devre Tasarımı ve Boyut Optimizasyonu]]
 
|- valign="top
 
|- valign="top
 
| '''authors''':
 
| '''authors''':
| Omercan Susam and [[Mustafa Altun]]
+
| Ceylan Morgul and [[Mustafa Altun]]
 
|- valign="top"
 
|- valign="top"
 
| '''presented at''':
 
| '''presented at''':
Line 705: Line 693:
 
<span class="plainlinks">
 
<span class="plainlinks">
  
[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/5/59/Susam_Altun_Kuantum_Devre_Sentezi_ve_Optimizasyonu_icin_Verimli_Bir_Algoritma.pdf]]</span>
+
[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/9/99/Morgul_Altun_Anahtarlamali_Nano_Dizinler_ile_Lojik_Devre_Tasarimi_ve_Boyut_Optimizasyonu.pdf]]</span>
 
<br>
 
<br>
[[Media:Susam_Altun_Kuantum_Devre_Sentezi_ve_Optimizasyonu_icin_Verimli_Bir_Algoritma.pdf  | Paper]]
+
[[Media:Morgul_Altun_Anahtarlamali_Nano_Dizinler_ile_Lojik_Devre_Tasarimi_ve_Boyut_Optimizasyonu.pdf  | Paper]]
  
 
| align="center" width="70" |
 
| align="center" width="70" |
 
<span class="plainlinks">
 
<span class="plainlinks">
  
[[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/3/38/Susam_Altun_Kuantum_Devre_Sentezi_ve_Optimizasyonu_icin_Verimli_Bir_Algoritma.pptx]]
+
[[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/a/aa/Morgul_Altun_Anahtarlamali_Nano_Dizinler_ile_Lojik_Devre_Tasarimi_ve_Boyut_Optimizasyonu.pptx]]
 
</span>
 
</span>
<br> [http://www.ecc.itu.edu.tr/images/3/38/Susam_Altun_Kuantum_Devre_Sentezi_ve_Optimizasyonu_icin_Verimli_Bir_Algoritma.pptx Slides]
+
<br> [http://www.ecc.itu.edu.tr/images/a/aa/Morgul_Altun_Anahtarlamali_Nano_Dizinler_ile_Lojik_Devre_Tasarimi_ve_Boyut_Optimizasyonu.pptx Slides]
 
|}
 
|}
  
Line 778: Line 766:
 
|- valign=top
 
|- valign=top
 
| '''presented&nbsp;at''':
 
| '''presented&nbsp;at''':
| [http://www.isvlsi.org/ IEEE Computer Society Annual Symposium on VLSI (ISVLSI)], Pittsburgh, USA, 2016.
+
| [http://www.eng.ucy.ac.cy/theocharides/isvlsi16/ IEEE Computer Society Annual Symposium on VLSI (ISVLSI)], Pittsburgh, USA, 2016.
 
|}
 
|}
  
Line 830: Line 818:
  
 
== Approximate Computing ==
 
== Approximate Computing ==
 +
 +
{| style="border:2px solid #abd5f5; background:#f1f5fc;"
 +
|
 +
{|
 +
|- valign=top
 +
| width="100" |'''title''':
 +
| width="550"|[[Media:Nojehdeh_Aksoy_Altun_Approximate_ANN.pdf | Efficient Hardware Implementation of Artificial Neural Networks Using Approximate Multiply-Accumulate Blocks]]
 +
|- valign="top"
 +
| '''authors''':
 +
| Mohammadreza Nojehdeh, Levent Aksoy, and [[Mustafa Altun]]
 +
|- valign=top
 +
| '''presented&nbsp;at''':
 +
| [http://www.eng.ucy.ac.cy/theocharides/isvlsi20/ IEEE Computer Society Annual Symposium on VLSI (ISVLSI)], Limassol, Cyprus, 2020.
 +
|}
 +
 +
| align=center width="70" |
 +
<span class="plainlinks">
 +
[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/b/bd/Nojehdeh_Aksoy_Altun_Approximate_ANN.pdf]]</span>
 +
<br>
 +
[[Media:Nojehdeh_Aksoy_Altun_Approximate_ANN.pdf | Paper]]
 +
| align="center" width="70" |
 +
<span class="plainlinks">
 +
 +
[[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/7/7f/Nojehdeh_Aksoy_Altun_Approximate_ANN.pptx]]
 +
</span>
 +
<br> [http://www.ecc.itu.edu.tr/images/7/7f/Nojehdeh_Aksoy_Altun_Approximate_ANN.pptx Slides]
 +
|}
  
 
{| style="border:2px solid #abd5f5; background:#f1f5fc;"
 
{| style="border:2px solid #abd5f5; background:#f1f5fc;"
Line 839: Line 854:
 
|- valign="top"
 
|- valign="top"
 
| '''authors''':
 
| '''authors''':
| Ceylan Morgul and [[Mustafa Altun]]
+
| Mohammadreza Nojehdeh and [[Mustafa Altun]]
 
|- valign="top"
 
|- valign="top"
| '''accepted&nbsp;in''':
+
| '''appeared&nbsp;in''':
| width="624" | [http://www.journals.elsevier.com/integration Integration, the VLSI Journal], 2019.
+
| width="624" | [http://www.journals.elsevier.com/integration Integration, the VLSI Journal], Vol. 70, pp. 99&ndash;107, 2020.
 
|}
 
|}
 
| align=center width="70" |  
 
| align=center width="70" |  
 
<span class="plainlinks">
 
<span class="plainlinks">
[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/5/58/Nojehdeh_Altun_Approximate_Adders_Multipliers.pdf]]</span>
+
[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/c/c8/Nojehdeh_Altun_Approximate_Adders_Multipliers.pdf]]</span>
 
<br>
 
<br>
 
[[Media:Nojehdeh_Altun_Approximate_Adders_Multipliers.pdf | Paper]]
 
[[Media:Nojehdeh_Altun_Approximate_Adders_Multipliers.pdf | Paper]]
 
|}
 
|}
 
  
 
{| style="border:2px solid #abd5f5; background:#f1f5fc; "
 
{| style="border:2px solid #abd5f5; background:#f1f5fc; "
Line 864: Line 878:
 
|- valign="top"
 
|- valign="top"
 
| '''appeared&nbsp;in''':
 
| '''appeared&nbsp;in''':
| [http://ieeeaccess.ieee.org/ IEEE Access], Vol. 7, pp. 4726&ndash;4734, 2019.
+
| [http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=6287639 IEEE Access], Vol. 7, pp. 4726&ndash;4734, 2019.
 
|}
 
|}
 
| align=center width="70" |
 
| align=center width="70" |
Line 913: Line 927:
 
|- valign=top
 
|- valign=top
 
| '''presented&nbsp;at''':
 
| '''presented&nbsp;at''':
| [http://www.isvlsi.org/ IEEE Computer Society Annual Symposium on VLSI (ISVLSI)], Bochum, Germany, 2017.
+
| [http://www.eng.ucy.ac.cy/theocharides/isvlsi17/ IEEE Computer Society Annual Symposium on VLSI (ISVLSI)], Bochum, Germany, 2017.
 
|}
 
|}
  
Line 997: Line 1,011:
  
 
=== Organic Transistor Modeling ===
 
=== Organic Transistor Modeling ===
 +
 +
{| style="border:2px solid #abd5f5; background:#f1f5fc; "
 +
 +
|
 +
{|
 +
|- valign=top
 +
| width="100" |'''title''':
 +
| width="624"|[[Media:Akkan_Altun_Sedef_OFET_Modelling_IEEE_Access.pdf| Modeling and Parameter Extraction of OFET Compact Models Using Metaheuristics-Based Approach
 +
]]
 +
|- valign="top"
 +
| '''authors''':
 +
| Nihat Akkan, [[Mustafa Altun]], and Herman Sedef
 +
|- valign="top"
 +
| '''appeared&nbsp;in''':
 +
| [http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=6287639 IEEE Access], Vol. 7, pp. 180438&ndash;180450, 2019.
 +
|}
 +
| align=center width="70" |
 +
<span class="plainlinks">
 +
[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/5/5c/Akkan_Altun_Sedef_OFET_Modelling_IEEE_Access.pdf]]</span>
 +
<br>
 +
[[Media:Akkan_Altun_Sedef_OFET_Modelling_IEEE_Access.pdf | Paper]]
 +
 +
|}
  
 
{| style="border:2px solid #abd5f5; background:#f1f5fc;"
 
{| style="border:2px solid #abd5f5; background:#f1f5fc;"
Line 1,024: Line 1,061:
 
</span>
 
</span>
 
<br> [http://www.ecc.itu.edu.tr/images/b/b9/Akkan_Altun_Sedef_OFET_Parameter_Extraction_with_ABC.pptx Slides]
 
<br> [http://www.ecc.itu.edu.tr/images/b/b9/Akkan_Altun_Sedef_OFET_Parameter_Extraction_with_ABC.pptx Slides]
 +
|}
 +
 +
== Reversible Computing ==
 +
 +
=== CMOS Fault Tolerance ===
 +
 +
{| style="border:2px solid #abd5f5; background:#f1f5fc; "
 +
 +
|
 +
{|
 +
|- valign=top
 +
| width="100" |'''title''':
 +
| width="624"|[[Media:Parvin_Altun_Perfect_Concurrent_Fault_Detection.pdf| Perfect Concurrent Fault Detection in CMOS Logic Circuits Using Parity Preservative Reversible Gates
 +
]]
 +
|- valign="top"
 +
| '''authors''':
 +
| Sajjad Parvin and [[Mustafa Altun]]
 +
|- valign="top"
 +
| '''appeared&nbsp;in''':
 +
| [http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=6287639 IEEE Access], Vol. 7, pp. 163939&ndash;163947, 2019.
 +
|}
 +
| align=center width="70" |
 +
<span class="plainlinks">
 +
[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/3/3c/Parvin_Altun_Perfect_Concurrent_Fault_Detection.pdf]]</span>
 +
<br>
 +
[[Media:Parvin_Altun_Perfect_Concurrent_Fault_Detection.pdf | Paper]]
 +
 +
|}
 +
 +
{| style="border:2px solid #abd5f5; background:#f1f5fc;"
 +
 +
|
 +
{|
 +
|- valign=top
 +
| width="100" |'''title''':
 +
| width="550"|[[Media:Parvin_Altun_CMOS_Fault_Tolerance_with_Preservative_Reversible_Gates.pdf | Implementation of CMOS Logic Circuits with Perfect Fault Detection Using Preservative Reversible Gates]]
 +
|- valign="top"
 +
| '''authors''':
 +
| Sajjad Parvin and [[Mustafa Altun]]
 +
|- valign=top
 +
| '''presented&nbsp;at''':
 +
| width="550"| [http://tima.univ-grenoble-alpes.fr/conferences/iolts/iolts19/ IEEE International Symposium on On-Line Testing and Robust System Design (IOLTS)], Rhodes Island, Greece, 2019.
 +
|}
 +
 +
| align=center width="70" |
 +
<span class="plainlinks">
 +
[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/e/ee/Parvin_Altun_CMOS_Fault_Tolerance_with_Preservative_Reversible_Gates.pdf]]</span>
 +
<br>
 +
[[Media:Parvin_Altun_CMOS_Fault_Tolerance_with_Preservative_Reversible_Gates.pdf | Paper]]
 +
| align="center" width="70" |
 +
<span class="plainlinks">
 +
 +
[[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/f/f4/Parvin_Altun_CMOS_Fault_Tolerance_with_Preservative_Reversible_Gates.pptx]]
 +
</span>
 +
<br> [http://www.ecc.itu.edu.tr/images/f/f4/Parvin_Altun_CMOS_Fault_Tolerance_with_Preservative_Reversible_Gates.pptx Poster]
 +
|}
 +
 +
{| style="border:2px solid #abd5f5; background:#f1f5fc; "
 +
 +
|
 +
{|
 +
|- valign=top
 +
| width="100" |'''title''':
 +
| width="624"|[[Media:Altun_Parvin_Cilasun_Exploiting_Reversible_Computing_for_CMOS_Fault_Tolerance.pdf| Exploiting Reversible Computing for Latent-Fault-Free Error Detecting/Correcting CMOS Circuits
 +
]]
 +
|- valign="top"
 +
| '''authors''':
 +
| [[Mustafa Altun]], Sajjad Parvin, and Husrev Cilasun
 +
|- valign="top"
 +
| '''appeared&nbsp;in''':
 +
| [http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=6287639 IEEE Access], Vol. 6, pp. 74475&ndash;74484, 2018.
 +
|}
 +
| align=center width="70" |
 +
<span class="plainlinks">
 +
[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/7/7d/Altun_Parvin_Cilasun_Exploiting_Reversible_Computing_for_CMOS_Fault_Tolerance.pdf]]</span>
 +
<br>
 +
[[Media:Altun_Parvin_Cilasun_Exploiting_Reversible_Computing_for_CMOS_Fault_Tolerance.pdf | Paper]]
 +
 +
|}
 +
 +
{| style="border:2px solid #abd5f5; background:#f1f5fc; "
 +
 +
|
 +
{|
 +
|- valign=top
 +
| width="100" |'''title''':
 +
| width="624"|[[Media:Cilasun_Altun_A_Novel_Reversible_Fault_Tolerant_Microprocessor.pdf| A Novel Reversible Fault Tolerant Microprocessor Design in AMS 0.35um Process
 +
]]
 +
|- valign="top"
 +
| '''authors''':
 +
| Husrev Cilasun and [[Mustafa Altun]]
 +
|- valign="top"
 +
| '''appeared&nbsp;in''':
 +
| [http://www.journals.istanbul.edu.tr/iujeee/index Istanbul University - Journal of Electrical & Electronics Engineering], Vol. 17, No. 1, pp. 3147&ndash;3154,  2017.
 +
|}
 +
| align=center width="70" |
 +
<span class="plainlinks">
 +
[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/3/30/Cilasun_Altun_A_Novel_Reversible_Fault_Tolerant_Microprocessor.pdf]]</span>
 +
<br>
 +
[[Media:Cilasun_Altun_A_Novel_Reversible_Fault_Tolerant_Microprocessor.pdf | Paper]]
 +
 +
|}
 +
 +
=== Logic Synthesis ===
 +
 +
{| style="border:2px solid #abd5f5; background:#f1f5fc; "
 +
 +
|
 +
{|
 +
|- valign=top
 +
| width="100" |'''title''':
 +
| width="624"|[[Media:Susam_Altun_Fast_Synthesis_of_Reversible_Circuits_using_a_Sorting_Algorithm_and_Optimization.pdf| Fast Synthesis of Reversible Circuits using a Sorting Algorithm and Optimization]]
 +
|- valign="top"
 +
| '''authors''':
 +
| Omercan Susam and [[Mustafa Altun]]
 +
|- valign="top"
 +
| '''appeared&nbsp;in''':
 +
| [http://www.oldcitypublishing.com/journals/mvlsc-home/ Journal of Multiple-Valued Logic and Soft Computing], Vol. 29, Issue 1-2, pp. 1&ndash;23, 2017.
 +
|}
 +
| align=center width="70" |
 +
<span class="plainlinks">
 +
[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/c/cd/Susam_Altun_Fast_Synthesis_of_Reversible_Circuits_using_a_Sorting_Algorithm_and_Optimization.pdf]]</span>
 +
<br>
 +
[[Media:Susam_Altun_Fast_Synthesis_of_Reversible_Circuits_using_a_Sorting_Algorithm_and_Optimization.pdf | Paper]]
 +
 +
|}
 +
 +
{| style="border:2px solid #abd5f5; background:#f1f5fc;"
 +
 +
|
 +
{|
 +
|- valign=top
 +
| width="100" |'''title''':
 +
| width="550"|[[Media:Susam_Altun_An_Efficient_Algorithm_to_Synthesize_Quantum_Circuits_and_Optimization.pdf| An Efficient Algorithm to Synthesize Quantum Circuits and Optimization]]
 +
|- valign="top"
 +
| '''authors''':
 +
| Omercan Susam and [[Mustafa Altun]]
 +
|- valign="top"
 +
| '''presented&nbsp;at''':
 +
| width="550"| [http://www.ieee-icecs2014.org/ IEEE International Conference on Electronics Circuits and Systems (ICECS)], Marseille, France, 2014.
 +
|}
 +
| align=center width="70" |
 +
<span class="plainlinks">
 +
[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/7/71/Susam_Altun_An_Efficient_Algorithm_to_Synthesize_Quantum_Circuits_and_Optimization.pdf]]</span>
 +
<br>
 +
[[Media:Susam_Altun_An_Efficient_Algorithm_to_Synthesize_Quantum_Circuits_and_Optimization.pdf | Paper]]
 +
| align="center" width="70" |
 +
<span class="plainlinks">
 +
 +
[[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/d/d0/Susam_Altun_An_Efficient_Algorithm_to_Synthesize_Quantum_Circuits_and_Optimization.pptx]]
 +
</span>
 +
<br> [http://www.ecc.itu.edu.tr/images/d/d0/Susam_Altun_An_Efficient_Algorithm_to_Synthesize_Quantum_Circuits_and_Optimization.pptx Slides]
 +
|}
 +
 +
==== National Publications in Turkish ====
 +
 +
{| style="border:2px solid #abd5f5; background:#f1f5fc;"
 +
 +
|
 +
{|
 +
|- valign=top
 +
| width="100" |'''title''':
 +
| width="550"|[[Media:Susam_Altun_Kuantum_Devre_Sentezi_ve_Optimizasyonu_icin_Verimli_Bir_Algoritma.pdf | Kuantum Devre Sentezi ve Optimizasyonu için Verimli bir Algoritma]]
 +
|- valign="top
 +
| '''authors''':
 +
| Omercan Susam and [[Mustafa Altun]]
 +
|- valign="top"
 +
| '''presented at''':
 +
| width="550"| [http://www.eleco.org.tr/ Elektrik, Elektronik, Bilgisayar ve Biyomedikal Mühendisliği Sempozyumu (ELECO)], Bursa, Turkey, 2014.
 +
|}
 +
 +
| align=center width="70" |
 +
<span class="plainlinks">
 +
 +
[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/5/59/Susam_Altun_Kuantum_Devre_Sentezi_ve_Optimizasyonu_icin_Verimli_Bir_Algoritma.pdf]]</span>
 +
<br>
 +
[[Media:Susam_Altun_Kuantum_Devre_Sentezi_ve_Optimizasyonu_icin_Verimli_Bir_Algoritma.pdf  | Paper]]
 +
 +
| align="center" width="70" |
 +
<span class="plainlinks">
 +
 +
[[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/3/38/Susam_Altun_Kuantum_Devre_Sentezi_ve_Optimizasyonu_icin_Verimli_Bir_Algoritma.pptx]]
 +
</span>
 +
<br> [http://www.ecc.itu.edu.tr/images/3/38/Susam_Altun_Kuantum_Devre_Sentezi_ve_Optimizasyonu_icin_Verimli_Bir_Algoritma.pptx Slides]
 
|}
 
|}
  

Latest revision as of 17:29, 19 October 2020

Listed below are the papers, first authored by our group members as an indication that the related research is mainly conducted in our group, and the presentations. Research topics are ordered from newest to oldest as well as by considering their importance. Under each topic, papers are ordered from newest to oldest. All materials are subject to copyrights.

Contents

[edit] Computing with Switching Lattices

[edit] Technology Development

title: Technology Development and Modeling of Switching Lattices Using Square and H Shaped Four-Terminal Switches
authors: Nihat Akkan, Serzat Safaltin, Levent Aksoy, Ismail Cevik, Herman Sedef, Csaba Andras Moritz, and Mustafa Altun
appeared in: IEEE Transactions on Emerging Topics in Computing, early access, 2020.

PDF.png
Paper

title: CMOS Implementation of Switching Lattices
authors: Ismail Cevik, Levent Aksoy, and Mustafa Altun
presented at: Design, Automation, and Test in Europe (DATE), Grenoble, France, 2020.

PDF.png
Paper

PPT.jpg
Slides

title: Realization of Four-Terminal Switching Lattices: Technology Development and Circuit Modeling
authors: Serzat Safaltin, Oguz Gencer, Ceylan Morgul, Levent Aksoy, Sebahattin Gurmen, Csaba Andras Moritz, and Mustafa Altun
presented at: Design, Automation and Test in Europe (DATE), Florence, Italy, 2019.

PDF.png
Paper

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[edit] Logic Synthesis and Fault/Variation Tolerance

title: A Novel Method for the Realization of Complex Logic Functions Using Switching Lattices
authors: Levent Aksoy and Mustafa Altun
presented at: IEEE International Symposium on Circuits and Systems (ISCAS), Seville, Spain, 2020.

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title: Novel Methods for Efficient Realization of Logic Functions Using Switching Lattices
authors: Levent Aksoy and Mustafa Altun
appeared in: IEEE Transactions on Computers, Vol. 69, Issue 3, pp. 427–440, 2020.

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title: A Satisfiability-Based Approximate Algorithm for Logic Synthesis Using Switching Lattices
authors: Levent Aksoy and Mustafa Altun
presented at: Design, Automation and Test in Europe (DATE), Florence, Italy, 2019.

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title: Optimal and Heuristic Algorithms to Synthesize Lattices of Four-Terminal Switches
authors: Ceylan Morgul and Mustafa Altun
appeared in: Integration, the VLSI Journal, Vol. 64, pp. 60–70, 2019.

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title: Logic Synthesis for Switching Lattices
authors: Mustafa Altun and Marc Riedel
appeared in: IEEE Transactions on Computers, Vol. 61, Issue 11, pp. 1588–1600, 2012.

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title: Synthesizing Logic with Percolation in Nanoscale Lattices
authors: Mustafa Altun and Marc Riedel
appeared in: International Journal of Nanotechnology and Molecular Computation, Vol. 3, Issue 2, pp. 12–30, 2011.

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title: Lattice Based Computation of Boolean Functions
authors: Mustafa Altun and Marc Riedel
presented at: IEEE/ACM Design Automation Conference (DAC), Anaheim, USA, 2010.

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title: Nanoscale Digital Computation Through Percolation
authors: Mustafa Altun, Marc Riedel, and Claudia Neuhauser
presented at: IEEE/ACM Design Automation Conference (DAC), San Francisco, USA, 2009.

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[edit] Energy Efficient ANN Hardware Implementation

title: Efficient Time-Multiplexed Realization of Feedforward Artificial Neural Networks
authors: Levent Aksoy, Sajjad Parvin, Mohammadreza Nojehdeh, and Mustafa Altun
presented at: IEEE International Symposium on Circuits and Systems (ISCAS), Seville, Spain, 2020.

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[edit] Computing with Nano-Crossbar Arrays

[edit] Comprehensive Performance Optimization

title: Nano-Crossbar based Computing: Lessons Learned and Future Directions
authors: Mustafa Altun, Ismail Cevik, Ahmet Erten, Osman Eksik, Mircea Stan, and Csaba Andras Moritz
presented at: Design, Automation, and Test in Europe (DATE), Grenoble, France, 2020.

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title: Integrated Synthesis Methodology for Crossbar Arrays
authors: Ceylan Morgul, Luca Frontini, Onur Tunali, Ioana Vatajelu, Valentina Ciriani, Lorena Anghel, Csaba Moritz, Mircea Stan, Dan Alexandrescu, and Mustafa Altun
presented at: IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH), Athens, Greece, 2018.

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title: Logic Synthesis and Defect Tolerance for Memristive Crossbar Arrays
authors: Onur Tunali and Mustafa Altun
presented at: Design, Automation and Test in Europe (DATE), Dresden, Germany, 2018.

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title: Logic Synthesis and Testing Techniques for Switching Nano-Crossbar Arrays
authors: Dan Alexandrescu, Mustafa Altun, Lorena Anghel, Anna Bernasconi, Valentina Ciriani, Luca Frontini, and Mehdi Tahoori
appeared in: Microprocessors and Microsystems, Vol. 54, pp. 14–25, 2017.

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title: Computing with Nano-Crossbar Arrays: Logic Synthesis and Fault Tolerance
authors: Mustafa Altun, Valentina Ciriani, and Mehdi Tahoori
presented at: Design, Automation and Test in Europe (DATE), Lausanne, Switzerland, 2017.

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title: Synthesis and Performance Optimization of a Switching Nano-crossbar Computer
authors: Dan Alexandrescu, Mustafa Altun, Lorena Anghel, Anna Bernasconi, Valentina Ciriani, and Mehdi Tahoori
presented at: Euromicro Conference on Digital System Design (DSD), Limassol, Cyprus, 2016.

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title: Power-Delay-Area Performance Modeling and Analysis for Nano-Crossbar Arrays
authors: Ceylan Morgul, Furkan Peker, and Mustafa Altun
presented at: IEEE Computer Society Annual Symposium on VLSI (ISVLSI), Pittsburgh, USA, 2016.

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[edit] Logic Synthesis and Fault/Variation Tolerance

title: A Fast Logic Mapping Algorithm for Multiple-type-Defect Tolerance in Reconfigurable Nano-Crossbar Arrays
authors: Onur Tunali and Mustafa Altun
appeared in: IEEE Transactions on Emerging Topics in Computing, Vol. 7, Issue 4, pp. 518–529, 2019.

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title: Defect Tolerant Logic Synthesis for Memristor Crossbars with Performance Evaluation
authors: Onur Tunali, Ceylan Morgul, and Mustafa Altun
appeared in: IEEE Micro, Vol. 38, Issue 5, pp. 22–31, 2018.

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title: A Fast Hill Climbing Algorithm for Defect and Variation Tolerant Logic Mapping of Nano-Crossbar Arrays
authors: Furkan Peker and Mustafa Altun
appeared in: IEEE Transactions on Multi-Scale Computing Systems, Vol. 4, No. 4, pp. 522–532, 2018.

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title: Yield Analysis of Nano-Crossbar Arrays for Uniform and Clustered Defect Distributions
authors: Onur Tunali and Mustafa Altun
presented at: IEEE International Conference on Electronics Circuits and Systems (ICECS), Batumi, Georgia, 2017.

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title: A Survey of Fault Tolerance Algorithms for Reconfigurable Nano-Crossbar Arrays
authors: Onur Tunali and Mustafa Altun
appeared in: ACM Computing Surveys, Vol. 50, No. 6, Article 79, 2017.

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title: Permanent and Transient Fault Tolerance for Reconfigurable Nano-Crossbar Arrays
authors: Onur Tunali and Mustafa Altun
appeared in: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 36, Issue 5, pp. 747–760, 2017.

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title: Defect Tolerance in Diode FET and Four-Terminal Switch Based Nano-Crossbar Arrays
authors: Onur Tunali and Mustafa Altun
presented at: IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH), Boston, USA, 2015.

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title: Synthesis and Optimization of Switching Nanoarrays
authors: Ceylan Morgul and Mustafa Altun
presented at: IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS), Belgrade, Serbia, 2015.

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[edit] National Publications in Turkish

title: Logic Circuit Design with Switching Nano Arrays and Area Optimization
title (in Turkish): Anahtarlamalı Nano Dizinler ile Lojik Devre Tasarımı ve Boyut Optimizasyonu
authors: Ceylan Morgul and Mustafa Altun
presented at: Elektrik, Elektronik, Bilgisayar ve Biyomedikal Mühendisliği Sempozyumu (ELECO), Bursa, Turkey, 2014.

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[edit] Stochastic and Bit Stream Computing

title: From Stochastic to Bit Stream Computing: Accurate Implementation of Arithmetic Circuits and Applications in Neural Networks
authors: Ensar Vahapoglu and Mustafa Altun
appeared in: arXiv, 1805.06262, 2018.

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title: Sampling Based Random Number Generator for Stochastic Computing
authors: Burak Karadeniz and Mustafa Altun
presented at: IEEE International Conference on Electronics Circuits and Systems (ICECS), Batumi, Georgia, 2017.

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title: Accurate Synthesis of Arithmetic Operations with Stochastic Logic
authors: Ensar Vahapoglu and Mustafa Altun
presented at: IEEE Computer Society Annual Symposium on VLSI (ISVLSI), Pittsburgh, USA, 2016.

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[edit] National Publications in Turkish

title: Random Bit Shuffling Method for Reducing Error Rates in Stochastic Computing
title (in Turkish): Stokastik Hesaplamada Hata Oranlarını Azaltmak için Rastgele Bit Karıştırma Yöntemi
authors: Serter Yavuz and Mustafa Altun
presented at: Elektrik, Elektronik, Bilgisayar ve Biyomedikal Mühendisliği Sempozyum (ELECO), Bursa, Turkey, 2014.

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[edit] Approximate Computing

title: Efficient Hardware Implementation of Artificial Neural Networks Using Approximate Multiply-Accumulate Blocks
authors: Mohammadreza Nojehdeh, Levent Aksoy, and Mustafa Altun
presented at: IEEE Computer Society Annual Symposium on VLSI (ISVLSI), Limassol, Cyprus, 2020.

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title: Systematic Synthesis of Approximate Adders and Multipliers with Accurate Error Calculations
authors: Mohammadreza Nojehdeh and Mustafa Altun
appeared in: Integration, the VLSI Journal, Vol. 70, pp. 99–107, 2020.

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Paper

title: Circuit Aware Approximate System Design with Case Studies in Image Processing and Neural Networks
authors: Tuba Ayhan and Mustafa Altun
appeared in: IEEE Access, Vol. 7, pp. 4726–4734, 2019.

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title: Approximate Fully Connected Neural Network Generation
authors: Tuba Ayhan and Mustafa Altun
presented at: International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD), Prague, Czech Republic, 2018.

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title: A Power Efficient System Design Methodology Employing Approximate Arithmetic Units
authors: Tuba Ayhan, Firat Kula, and Mustafa Altun
presented at: IEEE Computer Society Annual Symposium on VLSI (ISVLSI), Bochum, Germany, 2017.

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[edit] National Publications in Turkish

title: Approximate Implementation of FIR Filters on FPGA
title (in Turkish): FPGA Üzerinde Yaklaşık FIR Süzgeç Tasarımı
authors: Firat Kula, Tuba Ayhan, and Mustafa Altun
presented at: Sinyal İşleme ve İletişim Uygulamaları Kurultayı (SİU), Izmir, Turkey, 2018.

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[edit] Large-Area Electronics

[edit] Transistor Fabrication

title: The Enhanced Electronic Properties of P3HT-WO3 Hybrid Thin Film Transistors
authors: Beyza Yedikardes, Fereshteh Ordokhani, Nihat Akkan, Ece Kurt, Esra Zayim, Nilgün Yavuz, and Mustafa Altun
presented at: International Conference on Advanced Nanomaterials (ANM), Aveiro, Portugal, 2019.

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[edit] Organic Transistor Modeling

title: Modeling and Parameter Extraction of OFET Compact Models Using Metaheuristics-Based Approach

authors: Nihat Akkan, Mustafa Altun, and Herman Sedef
appeared in: IEEE Access, Vol. 7, pp. 180438–180450, 2019.

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title: Parameter Extraction Method Using Hybrid Artificial Bee Colony Algorithm for an OFET Compact Model
authors: Nihat Akkan, Mustafa Altun, and Herman Sedef
presented at: International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD), Prague, Czech Republic, 2018.

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[edit] Reversible Computing

[edit] CMOS Fault Tolerance

title: Perfect Concurrent Fault Detection in CMOS Logic Circuits Using Parity Preservative Reversible Gates

authors: Sajjad Parvin and Mustafa Altun
appeared in: IEEE Access, Vol. 7, pp. 163939–163947, 2019.

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title: Implementation of CMOS Logic Circuits with Perfect Fault Detection Using Preservative Reversible Gates
authors: Sajjad Parvin and Mustafa Altun
presented at: IEEE International Symposium on On-Line Testing and Robust System Design (IOLTS), Rhodes Island, Greece, 2019.

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title: Exploiting Reversible Computing for Latent-Fault-Free Error Detecting/Correcting CMOS Circuits

authors: Mustafa Altun, Sajjad Parvin, and Husrev Cilasun
appeared in: IEEE Access, Vol. 6, pp. 74475–74484, 2018.

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title: A Novel Reversible Fault Tolerant Microprocessor Design in AMS 0.35um Process

authors: Husrev Cilasun and Mustafa Altun
appeared in: Istanbul University - Journal of Electrical & Electronics Engineering, Vol. 17, No. 1, pp. 3147–3154, 2017.

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[edit] Logic Synthesis

title: Fast Synthesis of Reversible Circuits using a Sorting Algorithm and Optimization
authors: Omercan Susam and Mustafa Altun
appeared in: Journal of Multiple-Valued Logic and Soft Computing, Vol. 29, Issue 1-2, pp. 1–23, 2017.

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title: An Efficient Algorithm to Synthesize Quantum Circuits and Optimization
authors: Omercan Susam and Mustafa Altun
presented at: IEEE International Conference on Electronics Circuits and Systems (ICECS), Marseille, France, 2014.

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[edit] National Publications in Turkish

title: Kuantum Devre Sentezi ve Optimizasyonu için Verimli bir Algoritma
authors: Omercan Susam and Mustafa Altun
presented at: Elektrik, Elektronik, Bilgisayar ve Biyomedikal Mühendisliği Sempozyumu (ELECO), Bursa, Turkey, 2014.

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[edit] Reliability of Electronic Products

title: Distinct Degradation Processes in ZnO Varistors: Reliability Analysis and Modeling with Accelerated AC Tests
authors: Hadi Yadavari and Mustafa Altun
appeared in: Turkish Journal of Electrical Engineering and Computer Sciences, Vol. 25, No. 4, pp. 3240–3252, 2017.

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title: A Change-Point based Reliability Prediction Model using Field Return Data
authors: Mustafa Altun and Vehbi Comert
appeared in: Reliability Engineering and System Safety, Vol. 156, pp. 175–184, 2016.

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Paper

title: Effects of ZnO Varistor Degradation on the Overvoltage Protection Mechanism of Electronic Boards
authors: Hadi Yadavari, Burak Sal, Mustafa Altun, Ertunc Erturk, and Baris Ocak
presented at: European Safety and Reliability Conference (ESREL), Zurich, Switzerland, 2015.

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title: Extensive Investigation of Calibrated Accelerated Life Testing (CALT) in Comparison with Classical Accelerated Life Testing (ALT)
authors: Burak Sal and Mustafa Altun
presented at: European Safety and Reliability Conference (ESREL), Zurich, Switzerland, 2015.

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title: Warranty Forecasting of Electronic Boards using Short-term Field Data
authors: Vehbi Comert, Mustafa Altun, Mustafa Nadar, and Ertunc Erturk
presented at: Reliability and Maintainability Symposium (RAMS), Palm Harbor, USA, 2015.

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title: Reliability Prediction of Electronic Boards by Analyzing Field Return Data
authors: Vehbi Comert, Hadi Yadavari, Mustafa Altun, and Ertunc Erturk
presented at: European Safety and Reliability Conference (ESREL), Wroclaw, Poland, 2014.

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[edit] National Publications in Turkish

title: A New Reliability Model for MOSFET Gate Oxide Breakdown
title (in Turkish): MOSFET Geçit Oksidi Kırılması için Yeni Bir Güvenilirlik Modeli
authors: Hasan Avci and Mustafa Altun
presented at: Elektrik, Elektronik, Bilgisayar ve Biyomedikal Mühendisliği Sempozyumu (ELECO), Bursa, Turkey, 2018.

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[edit] Analog Circuit Design

title: Low Input Resistance Current Buffer Stage Using a Controllable Positive Feedback Loop, and Applications of Current Conveyor Based Filters
authors: Dogus Gungordu, Mustafa Altun, and Ismail Cevik
appeared  in: AEU International Journal of Electronics and Communications, Vol. 82, pp. 58–65, 2017.

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title: Design of Positive Feedback Driven Current-Mode Amplifiers Z-Copy CDBA and CDTA and Filter Applications
authors: Ersin Alaybeyoglu, Arda Guney, Mustafa Altun, and Hakan Kuntman
appeared  in: Analog Integrated Circuits and Signal Processing, Vol. 81, Issue 1, pp. 109–120, 2014.

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title: Realisation of nth Order Current Transfer Function Employing ECCIIs and Application Examples
authors: Mustafa Altun, Hakan Kuntman, Shahram Minaei, and Onur Sayin
appeared  in: International Journal of Electronics, Vol. 96, Issue 11, pp. 1115–1126, 2009.

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title: Design of a Fully Differential Current Mode Operational Amplifier with Improved Input-Output Impedances and its Filter Applications
authors: Mustafa Altun and Hakan Kuntman
appeared  in: AEU International Journal of Electronics and Communications, Vol. 62, Issue 3, pp. 39–44, 2008.

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Paper

title: A High Drive Fully Differential Current Mode Operational Amplifier Providing High Output Impedance and Filter Application
authors: Mustafa Altun and Hakan Kuntman
presented  at: International Conference on Electrical and Electronics Engineering (ELECO), Bursa, Turkey, 2007.

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Paper

title: High CMRR Current Mode Operational Amplifier with a Novel Class AB Input Stage
authors: Mustafa Altun and Hakan Kuntman
presented  at: ACM Great Lakes Symposium on VLSI (GLSVLSI), Stresa, Italy, 2007.

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Paper

title: A Wideband CMOS Current Mode Operational Amplifier and its Use for Band Pass Filter Realization
authors: Mustafa Altun and Hakan Kuntman
presented  at: Applied Electronics (AE), Pilsen, Czech Republic, 2006.

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[edit] National Publications in Turkish

title: Yüksek Başarımlı Tümüyle Farksal Akım Modlu İşlemsel Kuvvetlendirici (COA) Tasarımı ve Tüm Geçiren Süzgeç Yapısında Kullanımı
authors: Mustafa Altun and Hakan Kuntman
presented at: Elektrik, Elektronik, Bilgisayar ve Biyomedikal Mühendisliği Sempozyumu (ELECO), Bursa, Turkey, 2006.

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Paper

title: Akım Modlu İşlemsel Kuvvetlendirici Tasarımı ve Uygulamaları
title: Design of a Current Mode Operational Amplifier and Its Applications
author: Mustafa Altun
thesis: MSc, Electronics Engineering, Istanbul Technical University, 2007.

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[edit] Discrete Mathematics

title: A Study on Monotone Self-dual Boolean Functions
authors: Mustafa Altun and Marc Riedel
appeared  in: Acta Mathematicae Applicatae Sinica - English Series, Vol. 33, Issue 1, pp. 43–52, 2017.

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