EHB 205E

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|[[Media:ehb205e-2018-fall-hw-01.pdf | Homework 1]] & [[Media:ehb205e-2018-fall-hw-01-solutions.pdf | Solutions]] || [[Media:ehb205e-2018-fall-quiz-01.pdf | Quiz 1]] & [[Media:ehb205e-2018-fall-quiz-01-solutions.pdf | Solutions]]  ||  ||  [[Media:ehb205e-2018-fall-midterm-01.pdf | Midterm 1]]
 
|[[Media:ehb205e-2018-fall-hw-01.pdf | Homework 1]] & [[Media:ehb205e-2018-fall-hw-01-solutions.pdf | Solutions]] || [[Media:ehb205e-2018-fall-quiz-01.pdf | Quiz 1]] & [[Media:ehb205e-2018-fall-quiz-01-solutions.pdf | Solutions]]  ||  ||  [[Media:ehb205e-2018-fall-midterm-01.pdf | Midterm 1]]
 
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Revision as of 10:14, 13 November 2018

Contents

Announcements

  • Nov. 13th The second homework has been posted that is due 27/11/2018 before 13:30.
  • Oct. 2nd The first homework has been posted that is due 16/10/2018 before 13:30.
  • Sept. 30th The class is given in the room 5202 (second floor), EEF.

Syllabus

EHB 205E: Introduction to Logic Design, CRN: 12228, Tuesdays 13:30-16:30, Room: 5202 (EEF), Fall 2018.
Instructor

Mustafa Altun

  • Email: altunmus@itu.edu.tr
  • Tel: 02122856635
  • Office hours: 15:00 – 16:00 on Wednesdays in Room:3005, EEF (or stop by my office any time)
Teaching Assistant

Ensar Vahapoğlu

  • Email: ensarvahapoglu@gmail.com
  • Room: 3007 EEF
Grading
  • Quizzes: 10%
    • 2 pop-up quizzes (5% each) - no prior announcement of quiz dates and times
  • Homeworks: 10%
    • 4 homeworks (2.5% each)
  • Midterm Exams: 40%
    • 2 midterms (20% each) during the lecture time that will on 30/10/2018 and 4/12/2018.
  • Final Exam: 40%
Textbook
  • Wakerly, J. F. (20XX). Digital Design Principles & Practices. Prentice Hall.
Reference Books
  • Roth Jr, C., & Kinney, L. (20XX). Fundamentals of logic design. Cengage Learning.
  • Mano, M. M., & Kime, C. R. (20XX). Logic and Computer Design Fundamentals. Prentice Hall.
Policies
  • Homeworks are due at the beginning of class. Late homeworks will be downgraded by 20% for each day passed the due date.
  • Exams are in closed-notes and closed-books format.
  • To be eligible of taking the final or the resit exam, you should take both midterms and your midterm average should be at least 25 (out of 100).

Weekly Course Plan

Date
Topic
Week 1, 18/9/2018 Introduction
Week 2, 25/9/2018 Digital logic fundamentals: gates, combinational circuits, Boolean expressions
Week 3, 2/10/2018 Digital logic fundamentals: truth tables, two-level forms (AND/OR/NAND/NOR), "don't cares"
Weeks 4, 9/10/2018 Logic minimization: Karnaugh maps, Quine-McCluskey method
Weeks 5, 16/10/2018 Quine-McCluskey method, binary decision diagrams, hazards
Week 6, 23/10/2018 Combinational circuit design: building blocks (adders, multiplexers, decoders, etc.)
Weeks 7, 30/10/2018 MIDTERM I
Week 8, 6/11/2018 HOLIDAY, no class
Week 9, 13/11/2018 Combinational circuit design: implementing Boolean and arithmetic operations
Weeks 10, 20/11/2018 Area-Delay Performance analysis of combinational circuits
Week 11, 27/11/2018 Sequential circuits: latches & flip-flops
Week 12, 4/12/2018 MIDTERM II
Weeks 13, 11/12/2018 Sequential circuit design: state graphs and tables, modules
Weeks 14, 18/12/2018 Sequential circuit design: modules, state machines
Weeks 15, 25/12/2018 Sequential circuit design: modules, state machines

Course Materials

Homeworks & Solutions Quizzes & Solutions Sample Problems & Solutions Exams
Homework 1 & Solutions Quiz 1 & Solutions Midterm 1
Homework 2
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