BLG 231E
From The Emerging Circuits and Computation Group at ITU
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{{DISPLAYTITLE: BLG 231E: Digital Circuits}} | {{DISPLAYTITLE: BLG 231E: Digital Circuits}} | ||
== Announcements == | == Announcements == | ||
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+ | * <span style="background:#4682B4; color:#FFFFFF; font-size: 100%;"> Nov.11th</span> No class on November 10th due to [http://www.sis.itu.edu.tr/tr/duyuru/duyuru_detay.php?id=1068 the university's decision]. | ||
* <span style="background:#4682B4; color:#FFFFFF; font-size: 100%;"> Oct.21st</span> To see your final grades [[Media:blg231e-2017-fall-grades.pdf | '''click here''']]. | * <span style="background:#4682B4; color:#FFFFFF; font-size: 100%;"> Oct.21st</span> To see your final grades [[Media:blg231e-2017-fall-grades.pdf | '''click here''']]. |
Revision as of 12:55, 8 November 2017
Contents |
Announcements
- Nov.11th No class on November 10th due to the university's decision.
- Oct.21st To see your final grades click here.
- Oct. 10th The classroom is changed to 4102 (first floor), EEF.
- Sept. 22nd The first homework has been posted that is due 6/10/2017 before 9:30.
- Sept. 8th The class is given in the room 5305 (third floor), EEF.
Syllabus
BLG 231E: Digital Circuits, CRN: 13783, Fridays 09:30-12:30, Room: 4102 (EEF), Fall 2017.
Instructor
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Teaching Assistant
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Ensar Vahapoğlu
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Grading
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Textbook
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Reference Books
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Policies
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Weekly Course Plan
Date
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Topic
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Week 1, 15/9/2017 | Introduction |
Week 2, 22/9/2017 | Digital logic fundamentals: gates, combinational circuits, Boolean expressions |
Week 3, 29/9/2017 | Digital logic fundamentals: truth tables, two-level forms (AND/OR/NAND/NOR), "don't cares" |
Weeks 4, 6/10/2017 | Logic minimization: Karnaugh maps, Quine-McCluskey method |
Weeks 5, 13/10/2017 | Quine-McCluskey method, binary decision diagrams, hazards |
Week 6, 20/10/2017 | Combinational circuit design: building blocks (adders, multiplexers, decoders, etc.) |
Weeks 7, 27/10/2017 | MIDTERM I |
Week 8, 3/11/2017 | HOLIDAY, no class |
Week 9, 10/11/2017 | Combinational circuit design: implementing Boolean and arithmetic operations |
Weeks 10, 17/11/2017 | Area-Delay Performance analysis of combinational circuits |
Week 11, 24/11/2017 | Sequential circuits: latches & flip-flops |
Week 12, 1/12/2017 | MIDTERM II |
Weeks 13, 8/12/2017 | Sequential circuit design: state graphs and tables, modules |
Weeks 14, 15/12/2017 | Sequential circuit design: modules, state machines |
Weeks 15, 22/12/2017 | Sequential circuit design: modules, state machines |
Course Materials
Homeworks & Solutions | Quizzes & Solutions | Sample Problems & Solutions | Exams |
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Homework 1 & Solutions | Quiz 1 & Solutions | Problem Set 1 & Solutions | Midterm 1 |