BLG 231E

From The Emerging Circuits and Computation Group at ITU
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Revision as of 01:01, 5 October 2016

Contents

Announcements

  • Oct. 5th The first homework has been posted that is due 24/10/2015 before 9:30.
  • Aug. 26th The class is given in the room 5204 (second floor), EEF.

Syllabus

BLG 231E: Digital Circuits, CRN: 10647, Fridays 09:30-12:30, Room: 5204 (EEF), Fall 2016.
Instructor

Mustafa Altun

  • Email: altunmus@itu.edu.tr
  • Tel: 02122856635
  • Office hours: 15:00 – 16:00 on Tuesdays in Room:3005, EEF (or stop by my office any time)
Teaching Assistant

Furkan Peker

  • Email: furkan.peker061@gmail.com
  • Room: 3207 EEF

Ensar Vahapoğlu

  • Email: ensarvahapoglu@gmail.com
  • Room: 3007 EEF
Grading
  • Quizzes: 10%
    • 2 pop-up quizzes (5% each) - no prior announcement of quiz dates and times
  • Homeworks: 10%
    • 3 homeworks (3.3% each)
  • Midterm Exams: 40%
    • 2 midterms (20% each) during the lecture time that will on 4/11/2016 and 9/12/2016.
  • Final Exam: 40%
Textbook
  • Wakerly, J. F. (2005). Digital Design Principles & Practices, 4th edition. Prentice Hall.
Reference Books
  • Roth Jr, C., & Kinney, L. (2013). Fundamentals of logic design. Cengage Learning.
  • Mano, M. M., & Kime, C. R. (2008). Logic and Computer Design Fundamentals, 4/E edition, Prentice Hall.
Policies
  • Homeworks are due at the beginning of class. Late homeworks will be downgraded by 20% for each day passed the due date.
  • Exams are in closed-notes and closed-books format.
  • To be eligible of taking the final or the resit exam, you should take both midterms and your midterm average should be at least 25 (out of 100).

Weekly Course Plan

Date
Topic
Week 1, 23/9/2016 Introduction
Week 2, 30/9/2016 Digital logic fundamentals: gates, combinational circuits, Boolean expressions
Week 3, 7/10/2016 Digital logic fundamentals: truth tables, two-level forms (AND/OR/NAND/NOR), "don't cares"
Weeks 4, 14/10/2016 Logic minimization: Karnaugh maps, Quine-McCluskey method
Weeks 5, 21/10/2016 Quine-McCluskey method, binary decision diagrams, hazards
Week 6, 28/10/2016 Combinational circuit design: building blocks (adders, multiplexers, decoders, etc.)
Weeks 7, 4/11/2016 MIDTERM I
Week 8, 11/11/2016 HOLIDAY, no class
Week 9, 18/11/2016 Combinational circuit design: implementing Boolean and arithmetic operations
Weeks 10, 25/11/2016 Performance analysis of combinational circuits
Week 11, 2/12/2016 Sequential circuits: latches & flip-flops
Week 12, 9/12/2016 MIDTERM II
Weeks 13, 16/12/2016 Sequential circuit design: state graphs and tables, modules
Weeks 14, 23/12/2016 Sequential circuit design: modules, state machines
Weeks 15, 30/12/2016 Sequential circuit design: modules, state machines

Course Materials

Homeworks & Solutions Quizzes & Solutions Exams
Homework 1
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