BLG 231E

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== Announcements ==
 
== Announcements ==
  
* <span style="background:#4682B4; color:#FFFFFF; font-size: 100%;"> Jan. 13th</span> To see your final grades [[Media:blg231e-2015-fall-final-grades.pdf | '''click here''']].
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* <span style="background:#4682B4; color:#FFFFFF; font-size: 100%;"> Aug. 26th</span>  The class is given in the room '''5204''' (second floor), EEF.
* <span style="background:#4682B4; color:#FFFFFF; font-size: 100%;"> Dec. 26th</span> Final exam will be held in room '''5107''' between '''12:00 - 14:00''' on January 6th.
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* <span style="background:#4682B4; color:#FFFFFF; font-size: 100%;"> Dec. 6th</span> [[Media:blg231e-2015-fall-hw-03.pdf | '''The third homework''']] has been posted that is due '''22/12/2015''' before 13:30.
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* <span style="background:#4682B4; color:#FFFFFF; font-size: 100%;"> Nov. 30th</span> Midterm-2 will be held in room '''2106''' between '''13:30 - 15:30''' on December 1st.
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* <span style="background:#4682B4; color:#FFFFFF; font-size: 100%;"> Nov. 17th</span> [[Media:blg231e-2015-fall-hw-02.pdf | '''The second homework''']] has been posted that is due '''1/12/2015''' before 13:30.
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* <span style="background:#4682B4; color:#FFFFFF; font-size: 100%;"> Oct. 26th</span> Midterm-1 will be held in room '''2106''' between '''13:30 - 15:30'''.
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* <span style="background:#4682B4; color:#FFFFFF; font-size: 100%;"> Oct. 6th</span> [[Media:blg231e-2015-fall-hw-01.pdf | '''The first homework''']] has been posted that is due '''20/10/2015''' before 13:30.
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* <span style="background:#4682B4; color:#FFFFFF; font-size: 100%;"> Sept. 12th</span>  The class is given in the room '''2106''' (first floor), EEF.
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== Syllabus ==
 
== Syllabus ==
<div style="font-size: 120%;"> '''BLG 231E: Digital Circuits''', CRN: 12876, Tuesdays 13:30-16:30, Room: 2106 (EEF), Fall 2015. </div>  
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<div style="font-size: 120%;"> '''BLG 231E: Digital Circuits''', CRN: 10647, Fridays 09:30-12:30, Room: 5204 (EEF), Fall 2016. </div>  
 
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{| border="1" cellspacing="0" cellpadding="5" " width="80%"
 
    
 
    
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* Email: altunmus@itu.edu.tr
 
* Email: altunmus@itu.edu.tr
 
* Tel: 02122856635
 
* Tel: 02122856635
* Office hours: 15:00 – 16:30 on Thursdays in Room:3005, EEF (or stop by my office any time)
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* Office hours: 15:00 – 16:30 on Tuesdays in Room:3005, EEF (or stop by my office any time)
 
|-  
 
|-  
 
| <div style="font-size: 120%;"> '''Teaching Assistant'''</div>
 
| <div style="font-size: 120%;"> '''Teaching Assistant'''</div>
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* Email: furkan.peker061@gmail.com
 
* Email: furkan.peker061@gmail.com
 
* Room: 3207 EEF  
 
* Room: 3207 EEF  
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 +
Ensar Vahapoğlu
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* Email: ensarvahapoglu@gmail.com
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* Room: 3007 EEF
 
|-  
 
|-  
 
|  <div style="font-size: 120%;"> '''Grading'''</div>
 
|  <div style="font-size: 120%;"> '''Grading'''</div>

Revision as of 09:43, 26 August 2016

Contents

Announcements

  • Aug. 26th The class is given in the room 5204 (second floor), EEF.

Syllabus

BLG 231E: Digital Circuits, CRN: 10647, Fridays 09:30-12:30, Room: 5204 (EEF), Fall 2016.
Instructor

Mustafa Altun

  • Email: altunmus@itu.edu.tr
  • Tel: 02122856635
  • Office hours: 15:00 – 16:30 on Tuesdays in Room:3005, EEF (or stop by my office any time)
Teaching Assistant

Furkan Peker

  • Email: furkan.peker061@gmail.com
  • Room: 3207 EEF

Ensar Vahapoğlu

  • Email: ensarvahapoglu@gmail.com
  • Room: 3007 EEF
Grading
  • Homeworks: 15%
    • 3 homeworks (5% each)
  • Midterm Exams: 45%
    • 2 midterms (22.5% each) during the lecture time that will on 27/10/2015 and 1/12/2015.
  • Final Exam: 40%
Textbook
  • Wakerly, J. F. (2005). Digital Design Principles & Practices, 4th edition. Prentice Hall.
Reference Books
  • Roth Jr, C., & Kinney, L. (2013). Fundamentals of logic design. Cengage Learning.
  • Mano, M. M., & Kime, C. R. (2008). Logic and Computer Design Fundamentals, 4/E edition, Prentice Hall.
Policies
  • Homeworks are due at the beginning of class. Late homeworks will be downgraded by 20% for each day passed the due date.
  • Exams are in closed-notes and closed-books format.
  • To be eligible of taking the final or the resit exam, you should take both midterms and your midterm average should be at least 25 (out of 100).

Weekly Course Plan

Date
Topic
Week 1, 15/9/2015 Introduction
Week 2, 22/9/2015 HOLIDAY, no class
Week 3, 29/9/2015 Digital logic fundamentals: gates, combinational circuits, Boolean expressions
Weeks 4, 6/10/2015 Digital logic fundamentals: truth tables, two-level forms (AND/OR/NAND/NOR), "don't cares"
Weeks 5, 13/10/2015 Logic minimization: Karnaugh maps, Quine-McCluskey method
Week 6, 20/10/2015 Quine-McCluskey method, binary decision diagrams, hazards
Weeks 7, 27/10/2015 MIDTERM I
Week 8, 3/11/2015 Combinational circuit design: building blocks (adders, multiplexers, decoders, etc.)
Week 9, 10/11/2015 Combinational circuit design: implementing Boolean and arithmetic operations
Weeks 10, 17/11/2015 Performance analysis of combinational circuits
Week 11, 24/11/2015 Sequential circuits: latches & flip-flops
Week 12, 1/12/2015 MIDTERM II
Weeks 13, 8/12/2015 Sequential circuit design: state graphs and tables, modules
Weeks 14, 15/12/2015 Sequential circuit design: modules, state machines
Weeks 15, 22/12/2015 Sequential circuit design: modules, state machines

Course Materials

Homeworks & Solutions Exams
Homework 1 & Solutions Midterm 1
Homework 2 & Solutions Midterm 2
Homework 3 & Solutions Final
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