BLG 231E

From The Emerging Circuits and Computation Group at ITU
(Difference between revisions)
Jump to: navigation, search
(Announcements)
(Course Materials)
Line 107: Line 107:
 
|  [[Media:blg231e-2015-fall-hw-01.pdf | Homework 1]] & [[Media:blg231e-2015-fall-hw-01-solutions.pdf | Solutions]] ||  [[Media:blg231e-2015-fall-midterm-01.pdf | Midterm 1]]
 
|  [[Media:blg231e-2015-fall-hw-01.pdf | Homework 1]] & [[Media:blg231e-2015-fall-hw-01-solutions.pdf | Solutions]] ||  [[Media:blg231e-2015-fall-midterm-01.pdf | Midterm 1]]
 
|-  
 
|-  
| [[Media:blg231e-2015-fall-hw-02.pdf | Homework 2]] ||  [[Media:blg231e-2015-fall-midterm-02.pdf | Midterm 2]]
+
| [[Media:blg231e-2015-fall-hw-02.pdf | Homework 2]] & [[Media:blg231e-2015-fall-hw-02-solutions.pdf | Solutions]] ||  [[Media:blg231e-2015-fall-midterm-02.pdf | Midterm 2]]
 
|-
 
|-
 
| [[Media:blg231e-2015-fall-hw-03.pdf | Homework 3]] ||   
 
| [[Media:blg231e-2015-fall-hw-03.pdf | Homework 3]] ||   
 
|}
 
|}

Revision as of 10:46, 8 December 2015

Contents

Announcements

  • Dec. 6th The third homework has been posted that is due 22/12/2015 before 13:30.
  • Nov. 30th Midterm-2 will be held in room 2106 between 13:30 - 15:30 on December 1st.
  • Nov. 18th To see your grades click here.
  • Nov. 17th The second homework has been posted that is due 1/12/2015 before 13:30.
  • Oct. 26th Midterm-1 will be held in room 2106 between 13:30 - 15:30.
  • Oct. 6th The first homework has been posted that is due 20/10/2015 before 13:30.
  • Sept. 12th The class is given in the room 2106 (first floor), EEF.

Syllabus

BLG 231E: Digital Circuits, CRN: 12876, Tuesdays 13:30-16:30, Room: 2106 (EEF), Fall 2015.
Instructor

Mustafa Altun

  • Email: altunmus@itu.edu.tr
  • Tel: 02122856635
  • Office hours: 15:00 – 16:30 on Thursdays in Room:3005, EEF (or stop by my office any time)
Teaching Assistant

Furkan Peker

  • Email: furkan.peker061@gmail.com
  • Room: 3207 EEF
Grading
  • Homeworks: 15%
    • 3 homeworks (5% each)
  • Midterm Exams: 45%
    • 2 midterms (22.5% each) during the lecture time that will on 27/10/2015 and 1/12/2015.
  • Final Exam: 40%
Textbook
  • Wakerly, J. F. (2005). Digital Design Principles & Practices, 4th edition. Prentice Hall.
Reference Books
  • Roth Jr, C., & Kinney, L. (2013). Fundamentals of logic design. Cengage Learning.
  • Mano, M. M., & Kime, C. R. (2008). Logic and Computer Design Fundamentals, 4/E edition, Prentice Hall.
Policies
  • Homeworks are due at the beginning of class. Late homeworks will be downgraded by 20% for each day passed the due date.
  • Exams are in closed-notes and closed-books format.
  • To be eligible of taking the final or the resit exam, you should take both midterms and your midterm average should be at least 25 (out of 100).

Weekly Course Plan

Date
Topic
Week 1, 15/9/2015 Introduction
Week 2, 22/9/2015 HOLIDAY, no class
Week 3, 29/9/2015 Digital logic fundamentals: gates, combinational circuits, Boolean expressions
Weeks 4, 6/10/2015 Digital logic fundamentals: truth tables, two-level forms (AND/OR/NAND/NOR), "don't cares"
Weeks 5, 13/10/2015 Logic minimization: Karnaugh maps, Quine-McCluskey method
Week 6, 20/10/2015 Quine-McCluskey method, binary decision diagrams, hazards
Weeks 7, 27/10/2015 MIDTERM I
Week 8, 3/11/2015 Combinational circuit design: building blocks (adders, multiplexers, decoders, etc.)
Week 9, 10/11/2015 Combinational circuit design: implementing Boolean and arithmetic operations
Weeks 10, 17/11/2015 Performance analysis of combinational circuits
Week 11, 24/11/2015 Sequential circuits: latches & flip-flops
Week 12, 1/12/2015 MIDTERM II
Weeks 13, 8/12/2015 Sequential circuit design: state graphs and tables, modules
Weeks 14, 15/12/2015 Sequential circuit design: modules, state machines
Weeks 15, 22/12/2015 Sequential circuit design: modules, state machines

Course Materials

Homeworks & Solutions Exams
Homework 1 & Solutions Midterm 1
Homework 2 & Solutions Midterm 2
Homework 3
Personal tools
Namespaces

Variants
Actions
ECC
ECC (In Turkish)
Toolbox