BLG 231E

Revision as of 19:32, 7 September 2014

BLG 231E: Digital Circuits, CRN: 11043, Tuesdays 13:30-16:30, Room: 2104 (EEF), Fall 2014.

Instructor	Mustafa Altun Email: altunmus@itu.edu.tr Tel: 02122856635 Office hours: 15:00 – 16:30 on Thursdays in Room:3005, EEF (or stop by my office any time)
Teaching Assistant	Salih Vehbi Cömert Email: vehbicomert@gmail.com Room: 3009 EEF
Grading	Homeworks: 15% 3 homeworks (5% each) Midterm Exams: 40% 2 midterms (22.5% each) during the lecture time that will on 21/10/2014 and 25/11/2014. Final Exam: 40%
Textbook	Wakerly, J. F. (2005). Digital Design Principles & Practices, 4th edition. Prentice Hall.
Reference Book	Roth Jr, C., & Kinney, L. (2013). Fundamentals of logic design. Cengage Learning.
Policies	Homeworks are due at the beginning of class. Late homeworks will be downgraded by 20% for each day passed the due date. Exams are in closed-notes and closed-books format. To be eligible of taking the final or the resit exam, you should take both midterms and your midterm average should be at least 25 (out of 100).

Date	Topic
Week 1, 9/9/2014	Introduction
Week 2, 16/9/2014	Overview of emerging nanoscale devices and switches
Week 3, 23/9/2014	Quantum computing
Weeks 4, 30/9/2014	Molecular computing
Weeks 5, 7/10/2014	HOLIDAY!, no class
Week 6, 14/10/2014	Computing with nano arrays
Weeks 7, 21/10/2014	MIDTERM I
Week 8, 28/10/2014	Probabilistic computing
Week 9, 4/11/2014	Probabilistic computing
Weeks 10, 11/11/2014	Defects and reliability in nanoelectronics
Week 11, 18/11/2014	Defects and reliability in nanoelectronics
Week 12, 25/11/2014	MIDTERM II
Weeks 13, 2/12/2014	Student presentations
Weeks 14, 9/12/2014	Student presentations

@@ Line 29: / Line 29: @@
 * Midterm Exams: '''40%'''
-** 2 midterms (22.5% each) during the lecture time that will on 24/3/2014 and 28/4/2014.
+** 2 midterms (22.5% each) during the lecture time that will on 21/10/2014 and 25/11/2014.
 * Final Exam: '''40%'''