BLG 231E

From The Emerging Circuits and Computation Group at ITU
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(Syllabus)
(Syllabus)
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* Final Exam: '''40%'''
 
* Final Exam: '''40%'''
 
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|  <div style="font-size: 120%;"> '''Reference Books'''</div>
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|  <div style="font-size: 120%;"> '''Textbook'''</div>
 
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* Rabaey, J. M., Chandrakasan, A. P., & Nikolic, B. (2002). Digital integrated circuits. Englewood Cliffs: Prentice hall.
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* Wakerly, J. F. (2005). Digital Design Principles & Practices, 4th edition. Prentice Hall.
* Uyemura, J. P. (2002). CMOS logic circuit design. Springer.
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* Kang, S. M., & Leblebici, Y. (2003). Cmos Digital Integrated Circuits, 3/E. Tata McGraw-Hill Education.
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|  <div style="font-size: 120%;"> '''Reference Book'''</div>
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* Roth Jr, C., & Kinney, L. (2013). Fundamentals of logic design. Cengage Learning.
 
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|  <div style="font-size: 120%;"> '''Policies'''</div>
 
|  <div style="font-size: 120%;"> '''Policies'''</div>

Revision as of 19:26, 7 September 2014

Contents

Announcements

  • Sept. 7th The class is given in the room 2104 (first floor), EEF.

Syllabus

BLG 231E: Digital Circuits, CRN: 11043, Tuesdays 13:30-16:30, Room: 2104 (EEF), Fall 2014.
Instructor

Mustafa Altun

  • Email: altunmus@itu.edu.tr
  • Tel: 02122856635
  • Office hours: 15:00 – 16:30 on Thursdays in Room:3005, EEF (or stop by my office any time)
Teaching Assistant

Salih Vehbi Cömert

  • Email: vehbicomert@gmail.com
  • Room: 3009 EEF
Grading
  • Homeworks: 15%
    • 3 homeworks (5% each)
  • Midterm Exams: 40%
    • 2 midterms (22.5% each) during the lecture time that will on 24/3/2014 and 28/4/2014.
  • Final Exam: 40%
Textbook
  • Wakerly, J. F. (2005). Digital Design Principles & Practices, 4th edition. Prentice Hall.
Reference Book
  • Roth Jr, C., & Kinney, L. (2013). Fundamentals of logic design. Cengage Learning.
Policies
  • Homeworks are due at the beginning of class. Late homeworks will be downgraded by 20% for each day passed the due date.
  • Quizzes and exams are in closed-notes and closed-books format.
  • To be eligible of taking the final or the resit exam, you should take both midterms and your midterm average should be at least 25 (out of 100).

Weekly Course Plan

Date
Topic
Week 1, 10/2/2014 Introduction
Week 2, 17/2/2014 Devices for digital circuits and inverters
Week 3, 24/2/2014 NMOS/CMOS inverters & their static and dynamic behaviors
Weeks 4, 3/3/2014 Optimization of multiple-stage inverters and buffers
Weeks 5, 10/3/2014 Static logic gates
Week 6, 17/3/2014 Complex logic gates and their delays
Weeks 7, 24/3/2014 MIDTERM I
Week 8, 31/3/2014 Pass transistor logic
Week 9, 7/4/2014 Pass transistor logic & Dynamic logic gates
Weeks 10, 14/4/2014 Dynamic logic gates
Week 11, 21/4/2014 Flip-flops
Week 12, 28/4/2014 MIDTERM II
Weeks 13, 5/5/2014 Synchronization of digital circuits
Weeks 14, 12/5/2014 Semiconductor memories and gate arrays

Course Materials

Homeworks & Solutions Quizzes Exams
Homework 1 & Solutions Quiz 1 Midterm 1
Homework 2 & Solutions Quiz 2 Midterm 2
Homework 3
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