EHB 322E: Digital Electronic Circuits

Announcements

Apr. 11th The second homework has been posted that is due 22/04/2019 (before the lecture).

Mar. 18th The first midterm will be held on Monday Mar. 18th, between 15:30-17:30 in classrooms 5207 and 2102 in EEF.

Feb. 18th The first homework has been posted that is due 04/03/2019 (before the lecture).

Feb. 1st As a simulation tool, Spice is required for homeworks. Among different Spice-based programs, LTspice is a good and free choice; you can download it by clicking here.

EHB 322E: Digital Electronic Circuits, CRN: 20973, Mondays 13:30-16:30, Room: 5207 (EEF), Spring 2019.

Instructor	Mustafa Altun Email: altunmus@itu.edu.tr Tel: 02122856635 Office hours: 15:00 – 16:30 on Tuesdays in Room:3005, EEF
Teaching Assistant	Alican Çağlar Email: caglara@itu.edu.tr Room: 2311 EEF
Grading	Quizzes: 10% 2 pop-up quizzes (5% each) - no prior announcement of quiz dates and times Homeworks: 10% 3 homeworks (3.3% each) Midterm Exams: 40% 2 midterms (20% each) during the lecture time that will on 18/3/2019 and 29/4/2019. Final Exam: 40%
Reference Books	Rabaey, J. M., Chandrakasan, A. P., & Nikolic, B. (20XX). Digital integrated circuits. Englewood Cliffs: Prentice hall. Uyemura, J. P. (20XX). CMOS logic circuit design. Springer. Kang, S. M., & Leblebici, Y. (20XX). Cmos Digital Integrated Circuits. McGraw-Hill Education.
Policies	Homeworks are due at the beginning of class. Late homeworks will be downgraded by 20% for each day passed the due date. Quizzes and exams are in closed-notes and closed-books format. To be eligible of taking the final or the resit exam, your midterm average should be at least 25 (out of 100).

Date	Topic
Week 1, 4/2/2019	No class
Week 2, 11/2/2019	Introduction
Week 3, 18/2/2019	Switching theory & devices for digital circuits and inverters
Weeks 4, 25/2/2019	NMOS/CMOS inverters & their static and dynamic behaviors
Weeks 5, 4/3/2019	Optimization of multiple-stage inverters and buffers
Week 6, 11/3/2019	Static logic gates and area-delay-power performance analysis
Weeks 7, 18/3/2019	MIDTERM I
Week 8, 25/3/2019	HOLIDAY, no class
Week 9, 1/4/2019	Complex logic gates and their delays
Weeks 10, 8/4/2019	Pass transistor logic with Shannon's expansion and performance analysis
Week 11, 15/4/2019	Dynamic logic gates, synchronization, and performance analysis
Week 12, 22/4/2019	Static and dynamic memory elements: D, SR, and JK flip-flops
Weeks 13, 29/4/2019	MIDTERM II
Weeks 14, 6/5/2019	Synchronization and timing analysis of digital circuits having logic and memory elements
Weeks 15, 13/5/2019	Semiconductor memories and gate arrays: RAM's, ROM's, and flash memories