EHB 322E: Digital Electronic Circuits

Announcements

Feb. 24th The first homework has been posted that is due 09/03/2019 (before the lecture).
Feb. 10th As a simulation tool, Spice is required for homeworks. Among different Spice-based programs, LTspice is a good and free choice; you can download it by clicking here.

EHB 322E: Digital Electronic Circuits, CRN: 20991, Mondays 12:30-15:30, Room: 5102 (EEF), Spring 2020.

Instructor	Mustafa Altun Email: altunmus@itu.edu.tr Tel: 02122856635 Office hours: 15:00 – 16:30 on Tuesdays in Room:3005, EEF
Teaching Assistant	Sadık İlik Email: iliks@itu.edu.tr Room: 3105 EEF
Grading	Quizzes: 10% 2 pop-up quizzes (5% each) - no prior announcement of quiz dates and times Homeworks: 10% 3 homeworks (3.3% each) Midterm Exams: 40% 2 midterms (20% each) during the lecture time that will on 23/3/2020 and 27/4/2020. Final Exam: 40%
Reference Books	Weste, N., & Harris, D. (20XX). Integrated Circuit Design: International Version: A Circuits and Systems Perspective. Pearson Education,. Rabaey, J. M., Chandrakasan, A. P., & Nikolic, B. (20XX). Digital integrated circuits. Englewood Cliffs: Prentice hall. Uyemura, J. P. (20XX). CMOS logic circuit design. Springer. Kang, S. M., & Leblebici, Y. (20XX). Cmos Digital Integrated Circuits. McGraw-Hill Education.
Policies	Homeworks are due at the beginning of class. Late homeworks will be downgraded by 20% for each day passed the due date. Quizzes and exams are in closed-notes and closed-books format. To be eligible of taking the final or the resit exam, your midterm average should be at least 25 (out of 100).

Date	Topic
Week 1, 10/2/2020	Introduction
Week 2, 17/2/2020	Switching theory & devices for digital circuits and inverters
Weeks 3, 24/2/2020	NMOS/CMOS inverters & their static and dynamic behaviors
Weeks 4, 2/3/2020	Optimization of multiple-stage inverters and buffers
Week 5, 9/3/2020	Static logic gates and their area-delay-power performance analysis
Weeks 6, 16/3/2020	Complex logic gates and their area-delay-power performance analysis
Week 7, 23/3/2020	MIDTERM I
Week 8, 30/3/2020	HOLIDAY, no class
Weeks 9, 6/4/2020	Pass transistor logic with Shannon's expansion and performance analysis
Week 10, 13/4/2020	Dynamic logic gates, synchronization, and performance analysis
Week 10, 20/4/2020	Static and dynamic memory elements: D, SR, and JK flip-flops
Weeks 12, 27/4/2020	MIDTERM II
Weeks 13, 4/5/2020	Synchronization and timing analysis of digital circuits having logic and memory elements
Week 14, 11/5/2020	Semiconductor memories and gate arrays: RAM's, ROM's, and flash memories
Weeks 15, 18/5/2020	Semiconductor memories and gate arrays: RAM's, ROM's, and flash memories