EEF 205E

From The Emerging Circuits and Computation Group at ITU
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* Midterm Exams: '''50%'''
 
* Midterm Exams: '''50%'''
−
** 2 midterms (25% each) during the lecture time that will on '''15/11/2024''' and '''27/12/2024'''.
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** 2 midterms (25% each) during the lecture time that will on '''13/11/2026''' and '''18/12/2026'''.
  
 
* Final Exam: '''40%'''
 
* Final Exam: '''40%'''
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|| <div style="font-size: 120%;"> '''Topic'''</div>
 
|| <div style="font-size: 120%;"> '''Topic'''</div>
 
|-
 
|-
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|  Week  1, 4/10/2026      || Introduction
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|  Week  1, 2/10/2026      || Introduction
 
|-
 
|-
−
|  Week  2, 11/10/2026      || Digital logic fundamentals: gates, combinational circuits, Boolean expressions
+
|  Week  2, 9/10/2026      || Digital logic fundamentals: gates, combinational circuits, Boolean expressions
 
|-
 
|-
−
|  Week  3, 18/10/2026      || Digital logic fundamentals: truth tables, two-level forms (AND/OR/NAND/NOR), "don't cares"
+
|  Week  3, 16/10/2026      || Digital logic fundamentals: truth tables, two-level forms (AND/OR/NAND/NOR), "don't cares"
 
|-
 
|-
−
|  Weeks 4, 25/10/2026  || Logic minimization: Karnaugh maps, Quine-McCluskey method
+
|  Weeks 4, 23/10/2026  || Logic minimization: Karnaugh maps, Quine-McCluskey method
 
|-
 
|-
−
|  Weeks 5, 1/11/2026  || Logic minimization: Karnaugh maps, Quine-McCluskey method
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|  Weeks 5, 30/10/2026  || Logic minimization: Karnaugh maps, Quine-McCluskey method
 
|-
 
|-
−
|  Week 6, 8/11/2026      || Combinational circuit design: building blocks (adders, multiplexers, decoders, etc.)
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|  Week 6, 6/11/2026      || Combinational circuit design: building blocks (adders, multiplexers, decoders, etc.)
 
|-
 
|-
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|  Weeks 7, 15/11/2026  || MIDTERM I
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|  Weeks 7, 13/11/2026  || MIDTERM I
 
|-
 
|-
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|  Week  8, 22/11/2026    || HOLIDAY!
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|  Week  8, 20/11/2026    || HOLIDAY!
 
|-
 
|-
−
|  Week  9, 29/11/2026    || Combinational circuit design: implementing Boolean and arithmetic operations
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|  Week  9, 27/11/2026    || Combinational circuit design: implementing Boolean and arithmetic operations
 
|-
 
|-
−
|  Weeks 10, 6/12/2026 || Area-Delay Performance analysis of combinational circuits
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|  Weeks 10, 4/12/2026 || Sequential circuits: latches & flip-flops
 
|-
 
|-
−
|  Week  11, 13/12/2026      || Sequential circuits: latches & flip-flops
+
|  Week  11, 11/12/2026      || Sequential circuit design: state graphs and tables, modules
 
|-
 
|-
−
|  Week  12, 20/12/2026    || Sequential circuit design: state graphs and tables, modules
+
|  Week  12, 18/12/2026    || MIDTERM II
 
|-
 
|-
−
|  Weeks 13, 27/12/2026 || MIDTERM II
+
|  Weeks 13, 25/12/2026 || Sequential circuit design: modules, state machines
−
|-
+
−
|  Weeks 14, 3/1/2026 || Sequential circuit design: modules, state machines
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−
|-
+
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|  Weeks 15, 10/1/2026 || Sequential circuit design: modules, state machines
+
 
|}
 
|}
  

Revision as of 11:28, 23 September 2026


Syllabus

EEF 205E: Introduction to Logic Design, CRN: 14414, Fridays 8:30-11:30, Room: 6309 (EEF), Fall 2026.
Instructor

Mustafa Altun

  • Email: altunmus@itu.edu.tr
  • Tel: 02122856635
  • Office hours: 15:00 – 16:00 on Wednesdays in Room:3005, EEF (or stop by my office any time)
Teaching Assistant

İsmail Melik Türker

  • Email: turker16@itu.edu.tr
  • Room: 1105 EEF
Grading
  • Homeworks: 10%
    • 4 homeworks (2.5% each)
  • Midterm Exams: 50%
    • 2 midterms (25% each) during the lecture time that will on 13/11/2026 and 18/12/2026.
  • Final Exam: 40%
Textbook
  • Wakerly, J. F. (20XX). Digital Design Principles & Practices. Prentice Hall.
Reference Books
  • Roth Jr, C., & Kinney, L. (20XX). Fundamentals of logic design. Cengage Learning.
  • Mano, M. M., & Kime, C. R. (20XX). Logic and Computer Design Fundamentals. Prentice Hall.
Policies
  • Homeworks are due at the beginning of class. Late homeworks will be downgraded by 20% for each day passed the due date.
  • Exams are in closed-notes and closed-books format.
  • To be eligible of taking the final or the resit exam, your average, excluding the final, should be at least 40% of the class average.
  • To pass the class, your overall average should be at least 50% of the class average.

Weekly Course Plan

Date
Topic
Week 1, 2/10/2026 Introduction
Week 2, 9/10/2026 Digital logic fundamentals: gates, combinational circuits, Boolean expressions
Week 3, 16/10/2026 Digital logic fundamentals: truth tables, two-level forms (AND/OR/NAND/NOR), "don't cares"
Weeks 4, 23/10/2026 Logic minimization: Karnaugh maps, Quine-McCluskey method
Weeks 5, 30/10/2026 Logic minimization: Karnaugh maps, Quine-McCluskey method
Week 6, 6/11/2026 Combinational circuit design: building blocks (adders, multiplexers, decoders, etc.)
Weeks 7, 13/11/2026 MIDTERM I
Week 8, 20/11/2026 HOLIDAY!
Week 9, 27/11/2026 Combinational circuit design: implementing Boolean and arithmetic operations
Weeks 10, 4/12/2026 Sequential circuits: latches & flip-flops
Week 11, 11/12/2026 Sequential circuit design: state graphs and tables, modules
Week 12, 18/12/2026 MIDTERM II
Weeks 13, 25/12/2026 Sequential circuit design: modules, state machines

Course Materials

Shared through Ninova.

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