EHB 322E

Latest revision as of 14:01, 6 February 2026

EHB 322E: Digital Electronic Circuits, CRN: 22010, Mondays 12:30-15:30, Room: 4102 EEF, Spring 2026.

Instructor	Mustafa Altun Email: altunmus@itu.edu.tr Tel: 02122856635 Office hours: 15:00 – 16:00 on Wednesdays in Room:3005, EEF (or stop by my office any time) or online talk
Teaching Assistant	Fatma Betül Fişne Email: fisne20@itu.edu.tr
Grading	Quizzes: 10% 2 quizzes (5% each) - no prior announcement of quiz dates and times. Homeworks: 10% 2 homeworks (5% each) Midterm Exams: 40% 2 midterms (20% each) during the lecture time that will on 30/3/2026 and 4/5/2026. Final Exam: 40%
Reference Books	Weste, N., & Harris, D. (20XX). Integrated Circuit Design: International Version: A Circuits and Systems Perspective. Pearson Education,. Rabaey, J. M., Chandrakasan, A. P., & Nikolic, B. (20XX). Digital integrated circuits. Englewood Cliffs: Prentice hall. Uyemura, J. P. (20XX). CMOS logic circuit design. Springer. Kang, S. M., & Leblebici, Y. (20XX). Cmos Digital Integrated Circuits. McGraw-Hill Education.
Policies	Homeworks are due at the beginning of class. Late homeworks will be downgraded by 20% for each day passed the due date. Exams are in closed-notes and closed-books format. To be eligible of taking the final or the resit exam, you should take both midterms and your midterm average should be at least 25 (out of 100). The final exam will be same exam for all sections.

Date	Topic
Week 1, 9/2/2026	Introduction
Week 2, 16/2/2026	Switching theory & devices for digital circuits and inverters
Weeks 3, 23/2/2026	NMOS/CMOS inverters & their static and dynamic behaviors
Weeks 4, 2/3/2026	NMOS/CMOS inverters & their static and dynamic behaviors
Week 5, 9/3/2026	Optimization of multiple-stage inverters and buffers
Holiday Week, 16/3/2026	HOLIDAY, no class
Weeks 6, 23/3/2026	Static and complex logic gates and their area-delay-power performance analysis
Week 7, 30/3/2026	MIDTERM I
Weeks 8, 6/4/2026	Pass transistor logic with Shannon's expansion and performance analysis
Week 9, 13/4/2026	Dynamic logic gates performance analysis
Week 10, 20/4/2026	Dynamic logic gates, synchronization
Weeks 11, 27/4/2026	Static and dynamic memory elements: D, SR, and JK flip-flops
Weeks 12, 4/5/2026	MIDTERM II
Week 13, 11/5/2026	Synchronization and timing analysis of digital circuits having logic and memory elements
Weeks 14, 18/5/2026	Semiconductor memories and gate arrays: RAM's, ROM's, and flash memories

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 * Midterm Exams: '''40%'''
-** 2 midterms (20% each) during the lecture time that will on '''7/4/2025''' and '''12/5/2025'''.
+** 2 midterms (20% each) during the lecture time that will on '''30/3/2026''' and '''4/5/2026'''.
 * Final Exam: '''40%'''