BLG 231E

Revision as of 09:19, 6 October 2017

Sept. 22nd The first homework has been posted that is due 6/10/2017 before 9:30.

BLG 231E: Digital Circuits, CRN: 13783, Fridays 09:30-12:30, Room: 4102(EEF), Fall 2017.

Instructor	Mustafa Altun Email: altunmus@itu.edu.tr Tel: 02122856635 Office hours: 15:00 – 16:00 on Tuesdays in Room:3005, EEF (or stop by my office any time)
Teaching Assistant	Ensar Vahapoğlu Email: ensarvahapoglu@gmail.com Room: 3007 EEF
Grading	Quizzes: 10% 2 pop-up quizzes (5% each) - no prior announcement of quiz dates and times Homeworks: 10% 3 homeworks (3.3% each) Midterm Exams: 40% 2 midterms (20% each) during the lecture time that will on 27/10/2017 and 1/12/2017. Final Exam: 40%
Textbook	Wakerly, J. F. (20XX). Digital Design Principles & Practices. Prentice Hall.
Reference Books	Roth Jr, C., & Kinney, L. (20XX). Fundamentals of logic design. Cengage Learning. Mano, M. M., & Kime, C. R. (20XX). Logic and Computer Design Fundamentals. Prentice Hall.
Policies	Homeworks are due at the beginning of class. Late homeworks will be downgraded by 20% for each day passed the due date. Exams are in closed-notes and closed-books format. To be eligible of taking the final or the resit exam, you should take both midterms and your midterm average should be at least 25 (out of 100).

Date	Topic
Week 1, 15/9/2017	Introduction
Week 2, 22/9/2017	Digital logic fundamentals: gates, combinational circuits, Boolean expressions
Week 3, 29/9/2017	Digital logic fundamentals: truth tables, two-level forms (AND/OR/NAND/NOR), "don't cares"
Weeks 4, 6/10/2017	Logic minimization: Karnaugh maps, Quine-McCluskey method
Weeks 5, 13/10/2017	Quine-McCluskey method, binary decision diagrams, hazards
Week 6, 20/10/2017	Combinational circuit design: building blocks (adders, multiplexers, decoders, etc.)
Weeks 7, 27/10/2017	MIDTERM I
Week 8, 3/11/2017	HOLIDAY, no class
Week 9, 10/11/2017	Combinational circuit design: implementing Boolean and arithmetic operations
Weeks 10, 17/11/2017	Area-Delay Performance analysis of combinational circuits
Week 11, 24/11/2017	Sequential circuits: latches & flip-flops
Week 12, 1/12/2017	MIDTERM II
Weeks 13, 8/12/2017	Sequential circuit design: state graphs and tables, modules
Weeks 14, 15/12/2017	Sequential circuit design: modules, state machines
Weeks 15, 22/12/2017	Sequential circuit design: modules, state machines

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 == Syllabus ==
-<div style="font-size: 120%;"> '''BLG 231E: Digital Circuits''', CRN: 13783, Fridays 09:30-12:30, Room: 5305 (EEF), Fall 2017. </div>
+<div style="font-size: 120%;"> '''BLG 231E: Digital Circuits''', CRN: 13783, Fridays 09:30-12:30, Room: 4102(EEF), Fall 2017. </div>
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