BLG 231E

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|  Week  1, 10/2/2014      || Introduction  
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|  Week  1, 9/9/2014      || Introduction  
 
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|  Week  2, 17/2/2014      || Devices for digital circuits and inverters
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|  Week  2, 16/9/2014      || Overview of emerging nanoscale devices and switches
 
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|  Week  3, 24/2/2014      || NMOS/CMOS inverters & their static and dynamic behaviors
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|  Week  3, 23/9/2014      || Quantum computing
 
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|  Weeks 4, 3/3/2014  || Optimization of multiple-stage inverters and buffers
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|  Weeks 4, 30/9/2014  || Molecular computing
 
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|  Weeks 5, 10/3/2014  || Static logic gates
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|  Weeks 5, 7/10/2014  || HOLIDAY!, no class
 
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|  Week 6, 17/3/2014      || Complex logic gates and their delays
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|  Week 6, 14/10/2014      || Computing with nano arrays
 
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|  Weeks 7, 24/3/2014   || MIDTERM I  
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|  Weeks 7, 21/10/2014 || MIDTERM I  
 
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|  Week  8, 31/3/2014      || Pass transistor logic
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|  Week  8, 28/10/2014      || Probabilistic computing
 
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|  Week  9, 7/4/2014    || Pass transistor logic & Dynamic logic gates
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|  Week  9, 4/11/2014    || Probabilistic computing
 
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|  Weeks 10, 14/4/2014 || Dynamic logic gates
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|  Weeks 10, 11/11/2014 || Defects and reliability in nanoelectronics
 
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|  Week  11, 21/4/2014      || Flip-flops
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|  Week  11, 18/11/2014      || Defects and reliability in nanoelectronics
 
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|  Week  12, 28/4/2014    || MIDTERM II  
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|  Week  12, 25/11/2014    || MIDTERM II
 
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|  Weeks 13, 5/5/2014 || Synchronization of digital circuits
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|  Weeks 13, 2/12/2014 || Student presentations
 
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|  Weeks 14, 12/5/2014 || Semiconductor memories and gate arrays
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|  Weeks 14, 9/12/2014 || Student presentations
 
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Revision as of 19:31, 7 September 2014

Contents

Announcements

  • Sept. 7th The class is given in the room 2104 (first floor), EEF.

Syllabus

BLG 231E: Digital Circuits, CRN: 11043, Tuesdays 13:30-16:30, Room: 2104 (EEF), Fall 2014.
Instructor

Mustafa Altun

  • Email: altunmus@itu.edu.tr
  • Tel: 02122856635
  • Office hours: 15:00 – 16:30 on Thursdays in Room:3005, EEF (or stop by my office any time)
Teaching Assistant

Salih Vehbi Cömert

  • Email: vehbicomert@gmail.com
  • Room: 3009 EEF
Grading
  • Homeworks: 15%
    • 3 homeworks (5% each)
  • Midterm Exams: 40%
    • 2 midterms (22.5% each) during the lecture time that will on 24/3/2014 and 28/4/2014.
  • Final Exam: 40%
Textbook
  • Wakerly, J. F. (2005). Digital Design Principles & Practices, 4th edition. Prentice Hall.
Reference Book
  • Roth Jr, C., & Kinney, L. (2013). Fundamentals of logic design. Cengage Learning.
Policies
  • Homeworks are due at the beginning of class. Late homeworks will be downgraded by 20% for each day passed the due date.
  • Exams are in closed-notes and closed-books format.
  • To be eligible of taking the final or the resit exam, you should take both midterms and your midterm average should be at least 25 (out of 100).

Weekly Course Plan

Date
Topic
Week 1, 9/9/2014 Introduction
Week 2, 16/9/2014 Overview of emerging nanoscale devices and switches
Week 3, 23/9/2014 Quantum computing
Weeks 4, 30/9/2014 Molecular computing
Weeks 5, 7/10/2014 HOLIDAY!, no class
Week 6, 14/10/2014 Computing with nano arrays
Weeks 7, 21/10/2014 MIDTERM I
Week 8, 28/10/2014 Probabilistic computing
Week 9, 4/11/2014 Probabilistic computing
Weeks 10, 11/11/2014 Defects and reliability in nanoelectronics
Week 11, 18/11/2014 Defects and reliability in nanoelectronics
Week 12, 25/11/2014 MIDTERM II
Weeks 13, 2/12/2014 Student presentations
Weeks 14, 9/12/2014 Student presentations

Course Materials

Homeworks & Solutions Exams
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