Research

From The Emerging Circuits and Computation Group at ITU
(Difference between revisions)
Jump to: navigation, search
Line 426: Line 426:
 
| 2016-2017, ''completed''
 
| 2016-2017, ''completed''
 
|}
 
|}
   
+
{| style="margin-left: auto; margin-right: 0px; border:0.1px solid #abd5ff; background:#f1f5fc; padding:0.2em 0em;"
 +
|- valign="top"
 +
| width="140" |'''project goal''':
 +
| width="558"| Developing a synthesis methodology for online fault aware reversible circuits and their CMOS counterparts.
 +
 
 +
|}  
 
|}
 
|}
 
{| style="margin-left: auto; margin-right: 0px; border:1px solid #abd5f5; background:#f1f5fc;"
 
{| style="margin-left: auto; margin-right: 0px; border:1px solid #abd5f5; background:#f1f5fc;"
Line 535: Line 540:
 
| 2017-2020
 
| 2017-2020
 
|}
 
|}
 +
{| style="margin-left: auto; margin-right: 0px; border:0.1px solid #abd5ff; background:#f1f5fc; padding:0.2em 0em;"
 +
|- valign="top"
 +
| width="140" |'''project goal''':
 +
| width="558"| Improving accuracy in stochastic computing with implementing error–free aritmetic blocks, and using them in large-area electronics.
 +
 +
|}
 
|}
 
|}
  
Line 650: Line 661:
 
| '''duration''':
 
| '''duration''':
 
| 2017-2020
 
| 2017-2020
 +
|}
 +
{| style="margin-left: auto; margin-right: 0px; border:0.1px solid #abd5ff; background:#f1f5fc; padding:0.2em 0em;"
 +
|- valign="top"
 +
| width="140" |'''project goal''':
 +
| width="558"| Developing a hierarchical circuit/system design approach that can find solutions close to optimal solutions for power/energy consumption by determining the required accuracy performance of each circuit block, depending on the level of accuracy or quality desired from the system.
 
|}
 
|}
 
|}
 
|}
Line 813: Line 829:
 
| 2013-2015, ''completed''
 
| 2013-2015, ''completed''
 
|}
 
|}
+
{| style="margin-left: auto; margin-right: 0px; border:0.1px solid #abd5ff; background:#f1f5fc; padding:0.2em 0em;"
 +
|- valign="top"
 +
| width="140" |'''project goal''':
 +
| width="558"| Developing reliability prediction techniques for electronic cards of household appliances by using field return data, new accelerated test methodologies, and physics of failure based simulations.
 +
|}
 
|}
 
|}
 
{| style="margin-left: auto; margin-right: 0px; border:1px solid #abd5f5; background:#f1f5fc;"
 
{| style="margin-left: auto; margin-right: 0px; border:1px solid #abd5f5; background:#f1f5fc;"

Revision as of 12:38, 20 April 2019

Our research aims to develop novel ways of computing, circuit design, and reliability for electronic circuits and systems. Our research mainly targets emerging technologies and new computing paradigms. Listed below are the research topics, ordered from newest to oldest as well as by considering their importance. Each topic is explained briefly in support with related papers and projects.

Contents

Computing with Nano-Crossbar Arrays

Nano-crossbar arrays have emerged as a strong candidate technology to replace CMOS in near future. They are regular and dense structures. Computing with crossbar arrays is achieved by its crosspoints behaving as switches, either two-terminal or four-terminal. Depending on the technology used, a two-terminal switch behaves as a diode, a resistive/memristive switch, or a field effect transistor (FET). On the other hand, a four-terminal switch has a unique behavior. While there have been many different technologies proposed for two-terminal switch based arrays, technology development for four-terminal switch based arrays, called switching lattices, has recently started.

For both two-terminal and four-terminal switch based arrays, we aim to develop a complete synthesis and performance optimization methodology for switching nano-crossbar arrays that leads to the design and construction of an emerging nanocomputer. We also aim to develeop CMOS-compatible technologies for crossbar arrays, specifically for switching lattices.

Research nano-2019.png

Technology Development

Although a four-terminal switch based array offers a significant area advantage, in terms of the number of switches, compared to the ones having two-terminal switches, its realization at the technology level needs further justifications and raises a number of questions about its feasibility. We answer these questions. First, by using three dimensional technology computer-aided design (TCAD) simulations, we show that four-terminal switches can be directly implemented with the CMOS technology. For this purpose, we try different semiconductor gate materials in different formations of geometric shapes. Then, by fitting the TCAD simulation data to the standard CMOS current-voltage equations, we develop a Spice model of a four-terminal switch. Finally, we successfully perform Spice circuit simulations on four-terminal switches with different sizes.

Research lattice technology.png

Performance Optimization

We study crossbar arrys including the memristive ones. We propose a defect-tolerant logic synthesis algorithms by considering area, delay, and power costs of the arrays.

Fault Tolerance

We examine reconfigurable crossbar arrays by considering randomly occurred stuck-open and stuck-closed crosspoint faults. In the presence of permanent faults, a fast and accurate heuristic algorithm is proposed that uses the techniques of index sorting, backtracking, and row matching. In the presence of transient faults, tolerance analysis is performed by formally and recursively determining tolerable fault positions.

Synthesis

We study implementation of Boolean functions with nano-crossbar arrays where each crosspoint behaves as a diode, a FET, and a four-terminal switch. For these three types, we give array size formulations for a given Boolean function. Additionally, we focus on four-terminal switch based implementations and propose an algorithm that implements Boolean functions with optimal array sizes.

Selected Publications
title: Realization of Four-Terminal Switching Lattices: Technology Development and Circuit Modeling
authors: Serzat Safaltin, Oguz Gencer, Ceylan Morgul, Levent Aksoy, Sebahattin Gurmen, Csaba Andras Moritz, and Mustafa Altun
presented at: Design, Automation and Test in Europe (DATE), Florence, Italy, 2019.

PDF.png
Paper

PPT.jpg
Slides

title: Defect Tolerant Logic Synthesis for Memristor Crossbars with Performance Evaluation
authors: Onur Tunali and Mustafa Altun
appeared in: IEEE Micro, Vol. 38, Issue 5, pp. 22–31, 2018.
presented at: Design, Automation and Test in Europe (DATE), Dresden, Germany, 2018.

PDF.png
Paper

PPT.jpg
Slides

title: Logic Synthesis and Testing Techniques for Switching Nano-Crossbar Arrays
authors: Dan Alexandrescu, Mustafa Altun, Lorena Anghel, Anna Bernasconi, Valentina Ciriani, Luca Frontini, and Mehdi Tahoori
appeared in: Microprocessors and Microsystems, Vol. 54, pp. 14–25, 2017.
presented at: Euromicro Conference on Digital System Design (DSD), Limassol, Cyprus, 2016.

PDF.png
Paper

PDF.png
Slides

title: Permanent and Transient Fault Tolerance for Reconfigurable Nano-Crossbar Arrays
authors: Onur Tunali and Mustafa Altun
appeared in: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 36, Issue 5, pp. 747–760, 2017.
presented at: IEEE/ACM International Symposium on Nanoscale Architectures
(NANOARCH)
, Boston, USA, 2015.

PDF.png
Paper

PPT.jpg
Slides

Funding Projects
title: Computing with Switching Lattices: Technology Development, Device Modeling, and Circuit Design
agency & program: TUBITAK-NSF Joint Research Program (2501)
budget: 720.000 TL
duration: 2019-2022
project goal: Developing a new CMOS-compatible technology based on switching lattice structures and an EDA methodology that designs digital circuits with switching lattices.
title: Synthesis and Performance Optimization of a Switching Nano-Crossbar Computer
agency & program: European Union/European Commission H2020 MSCA Research and Innovation Staff Exchange Program (RISE)
budget: 724.500 EURO
duration: 2015-2019
project goal: Developing a complete synthesis methodology for nano-crossbar arrays, and implementing technology-dependent state machines that leads to the design and construction of an emerging computer.
title: Synthesis and Reliability Analysis of Nano Switching Arrays
agency & program: TUBITAK Career Program (3501)
budget: 190.000 TL
duration: 2014-2017, completed
project goal: Performing logic synthesis, fault tolerance, and performance optimization for nano-crossbar arrays.


Reversible Computing

Unlike conventional CMOS circuits, reversible circuits do not have latent faults, so faults occurring in internal circuit nodes always result in an error at the output. This is a unique feature for online or concurrent fault tolerance. Motivated by this, we implement error tolerant CMOS circuit blocks by exploiting reversible computing. We first synthesize reversible circuits with reversible gates; then we make them fault-tolerant; and finally we perform conversion from reversible gates to CMOS gates.


Research-reversible-2.png

Synthesis

We propose a fast synthesis algorithm that implements any given reversible Boolean function with reversible gates. Instead of an exhaustive search on every given function, our algorithm creates a library of essential functions and performs sorting. As an example, to implement 4 bit circuits we only use 120 essential functions out of all 20922789888000 functions. We also perform optimization for both reversible and quantum circuit costs by considering adjacent gate pairs.

Online Error Detection and Correction

We develop two techniques to make a reversible circuit fault-tolerant by using multiple-control Toffoli gates. The first technique is based on single parity preserving, and offers error detection for odd number of errors at the output. The second technique is constructed on Hamming codes for error correction. We also claim that perfect error detection is possible with conservative reversible gates such as a Fredkin gate. As the next step, we utilize the proposed reversible circuits with conventional CMOS gates.

Selected Publications
title: Exploiting Reversible Computing for Latent-Fault-Free Error Detecting/Correcting CMOS Circuits

authors: Mustafa Altun, Sajjad Parvin, and Husrev Cilasun
appeared in: IEEE Access, , Vol. 6, pp. 74475–74484, 2018.

PDF.png
Paper

title: Fast Synthesis of Reversible Circuits using a Sorting Algorithm and Optimization
authors: Omercan Susam and Mustafa Altun
appeared in: Journal of Multiple-Valued Logic and Soft Computing, Vol. 29, Issue 1-2, pp. 1–23, 2017.
presented at: IEEE International Conference on Electronics Circuits and Systems (ICECS), Marseille, France, 2014.

PDF.png
Paper

PPT.jpg
Slides

Funding Projects
title: Implementation of a Fault-Aware 8-Bit Reversible Microprocessor
agency & program: TUBITAK Short Term R&D Funding Program (1002)
budget: 30.000 TL
duration: 2016-2017, completed
project goal: Developing a synthesis methodology for online fault aware reversible circuits and their CMOS counterparts.
title: Quantum Circuit Design and Computation
agency & program: Istanbul Technical University Research Support Program (ITU-BAP)
duration: 2014-2015, completed


Stochastic Circuit Design

Accurate Arithmetic Implementations

We propose a method to overcome the main drawback in stochastic computing, low accuracy or related long computing times. Our method manipulates stochastic bit streams with the aid of feedback mechanisms. We implement error-free arithmetic multiplier and adder circuits by considering performance parameters area, delay, and accuracy.

Research-stochastic-1.png
Selected Publications
title: Accurate Synthesis of Arithmetic Operations with Stochastic Logic
authors: Ensar Vahapoglu and Mustafa Altun
presented at: IEEE Computer Society Annual Symposium on VLSI (ISVLSI), Pittsburgh, USA, 2016.

PDF.png
Paper

PPT.jpg
Poster

Funding Projects
title: Implementation of Accurate Stochastic Circuit Blocks and their Applications for Printed/Flexible Electronic Systems
agency & program: TUBITAK Scientific and Technological Research Projects Funding Program (1001)
budget: 260.000 TL
duration: 2017-2020
project goal: Improving accuracy in stochastic computing with implementing error–free aritmetic blocks, and using them in large-area electronics.
title: Gate and Transistor Implementations of Accurate Arithmetic Operation Blocks with Stochastic Logic
agency & program: Istanbul Technical University Research Support Program (ITU-BAP)
duration: 2017-2019


Approximate Circuit and System Design

Power/Area Efficient Approximate System Design Methodology

This work provides power/area efficiency of circuit-level design with accuracy supervision of system-level design. The proposed method selects approximate computational units that minimize the total computation cost, yet maintaining the ultimate performance. The method investigates the overall system from the highest level down to the arithmetic units to determine the sufficient output quality at each block.

Research-approximate.png
Selected Publications
title: Circuit Aware Approximate System Design with Case Studies in Image Processing and Neural Networks
authors: Tuba Ayhan and Mustafa Altun
appeared in: IEEE Access, Vol. 7, pp. 4726–4734, 2019.
presented at: IEEE Computer Society Annual Symposium on VLSI (ISVLSI), Bochum, Germany, 2017.

PDF.png
Paper

PPT.jpg
Slides

Funding Projects
title: Design of Reconfigurable Circuits and Systems that can Perform Approximate Computation and their Use in Image Processing Applications Involving Learning
agency & program: TUBITAK Scientific and Technological Research Projects Funding Program (1001)
budget: 230.000 TL
duration: 2017-2020
project goal: Developing a hierarchical circuit/system design approach that can find solutions close to optimal solutions for power/energy consumption by determining the required accuracy performance of each circuit block, depending on the level of accuracy or quality desired from the system.


Reliability of Electronic Products

The rapid developments in electronics, especially in the last decade, have elevated the importance of electronics reliability. Conventionally used accelerated reliability tests have lost their significance; time consuming and expensive feature of these tests is against the demands of today's very rapid electronic product cycles. In this study, we propose less costly, yet accurate, reliability prediction techniques using field return data, new accelerated test methodologies, and physics of failure based simulations. We cooperate with one of the Europe’s largest household appliance companies Arçelik A.Ş..

Research-3.png

Reliability Analysis and Prediction with Field Data

We propose an accurate reliability prediction model for high-volume electronic products throughout their warranty periods by using field return data. Our model is constructed on a Weibull-exponential hazard rate scheme by using the proposed change point detection method based on backward and forward data analysis. Our prediction model can make a 36-month (full warranty) reliability prediction of an electronic board with using its field data as short as 3 months.

Degradation Processes in Varistors

We investigate different degradation mechanisms of ZnO varistors. We propose a model showing how the varistor voltage Vv changes by time for different stress levels. For this purpose, accelerated degradation tests are applied for different AC current levels; then voltage values are measured. Different from the common practice in the literature that considers a degradation with only decreasing Vv values, we demonstrate either an increasing or a decreasing trend in the Vv parameter.

Calibrated Accelerated Life Testing

Dramatic decrease in failure rates for electronic products makes conventional accelerated life tests (ALT) extremely time consuming and costly. Recently proposed calibrated accelerated life tests (CALT) aim to use fewer samples than those used in ALT. We thoroughly compare ALT and CALT by considering the effects of failure rate, acceleration factor, and stress level on the required test time.

Selected Publications
title: A Change-Point based Reliability Prediction Model using Field Return Data
authors: Mustafa Altun and Vehbi Comert
appeared in: Reliability Engineering and System Safety, Vol. 156, pp. 175–184, 2016.
presented at: Reliability and Maintainability Symposium (RAMS), Palm Harbor, USA, 2015.

PDF.png
Paper

PPT.jpg
Slides

title: Distinct Degradation Processes in ZnO Varistors: Reliability Analysis and Modeling with Accelerated AC Tests
authors: Hadi Yadavari and Mustafa Altun
appeared in: Turkish Journal of Electrical Engineering and Computer Sciences, Vol. 25, No. 4, pp. 3240–3252, 2017.
presented at: European Safety and Reliability Conference (ESREL), Zurich, Switzerland, 2015.

PDF.png
Paper

PPT.jpg
Slides

title: Extensive Investigation of Calibrated Accelerated Life Testing (CALT) in Comparison with Classical Accelerated Life Testing (ALT)
authors: Burak Sal and Mustafa Altun
presented at: European Safety and Reliability Conference (ESREL), Zurich, Switzerland, 2015.

PDF.png
Paper

PPT.jpg
Slides

Funding Projects
title: An Accurate Reliability Methodology for Appliance Electronic Cards
agency & program: TUBITAK University-Industry Collaboration Grant Program (1505)
budget: 210.000 TL
duration: 2013-2015, completed
project goal: Developing reliability prediction techniques for electronic cards of household appliances by using field return data, new accelerated test methodologies, and physics of failure based simulations.
title: Gate Oxide Breakdown Failure Mechanism of CMOS Transistors
agency & program: TUBITAK Industry Oriented Senior Project Support Program (2241/A)
duration: 2013-2014, completed


Analog Circuit Design

Positive Feedback

The conventional wisdom is that analog circuits should not include positive feedback loops. As controversial as it seems, we have successfully used positive feedback for impedance improvement in a current amplifier. With adding few transistors we have achieved very low input resistance values. Additionally, we have proposed a new fully-differential current amplifier and tested it in a filter application.

Selected Publications
title: Design of a Fully Differential Current Mode Operational Amplifier with its Filter Applications
authors: Mustafa Altun and Hakan Kuntman
appeared in: AEU International Journal of Electronics and Communications, Vol. 62, Issue 3, pp. 39–44, 2008.
presented at: ACM Great Lakes Symposium on VLSI (GLSVLSI), Stresa, Italy, 2007.

PDF.png
Paper

PPT.jpg
Slides


Discrete Mathematics

Self Duality Problem

The problem of testing whether a monotone Boolean function in irredundant disjuntive normal form (IDNF) is self-dual is one of few problems in circuit/time complexity whose precise tractability status is unknown. We have focused on this famous problem. We have shown that monotone self-dual Boolean functions in IDNF do not have more variables than disjuncts. We have proposed an algorithm to test whether a monotone Boolean function in IDNF with n variables and n disjuncts is self-dual. The algorithm runs in O(n^3) time.

Selected Publications
title: A Study on Monotone Self-dual Boolean Functions
authors: Mustafa Altun and Marc Riedel
appeared  in: Acta Mathematicae Applicatae Sinica - English Series, Vol. 33, Issue 1, pp. 43–52, 2017.

PDF.png
Paper

PPT.jpg
Slides

Personal tools
Namespaces

Variants
Actions
ECC
ECC (In Turkish)
Toolbox