Research

From The Emerging Circuits and Computation Group at ITU
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Our research aims to develop novel ways of computing, circuit design, and reliability for electronic circuits and systems. Our research mainly targets emerging technologies and new computing paradigms.
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Our research aims to develop novel ways of computing, circuit design, and reliability for electronic circuits and systems. Our research mainly targets emerging technologies and new computing paradigms.
 +
Listed below are the research topics, ordered from newest to oldest as well as by considering their importance. Each topic is explained briefly in support with related papers and projects.  
  
 
<div style="float:center; font-size:110%; font-weight:bold; clear:both; padding:0; margin:0.0em;">__TOC__</div>
 
<div style="float:center; font-size:110%; font-weight:bold; clear:both; padding:0; margin:0.0em;">__TOC__</div>
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Fault Tolerance</h3>
 
Fault Tolerance</h3>
  
We examine reconfigurable crossbar arrays by considering randomly occurred '''stuck-open and stuck-closed crosspoint faults'''. In the presence of '''permanent''' faults, a fast and accurate heuristic algorithm is proposed that uses the techniques of index sorting, backtracking, and row matching. In the presence of '''transient''' faults, tolerance analysis is performed by formally and recursively determining tolerable fault positions
+
We examine reconfigurable crossbar arrays by considering randomly occurred '''stuck-open and stuck-closed crosspoint faults'''. In the presence of '''permanent''' faults, a fast and accurate heuristic algorithm is proposed that uses the techniques of index sorting, backtracking, and row matching. In the presence of '''transient''' faults, tolerance analysis is performed by formally and recursively determining tolerable fault positions.
  
 
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| Onur Tunali and [[Mustafa Altun]]
 
| Onur Tunali and [[Mustafa Altun]]
 
|- valign="top"
 
|- valign="top"
| '''accepted&nbsp;in''':
+
| '''appeared&nbsp;in''':
| [http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=43 IEEE Transactions on Computer-Aided Design of<br> Integrated Circuits and Systems], 2016.
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| width="450" | [http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=43 IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems], Vol. 36, Issue 5, pp. 747&ndash;760, 2017.
 
|- valign="top"
 
|- valign="top"
 
| '''presented&nbsp;at''':
 
| '''presented&nbsp;at''':
| [http://www.nanoarch.org/ IEEE/ACM International Symposium on Nanoscale Architectures<br> (NANOARCH)], Boston, USA, 2015.
+
| width="450"| [http://www.nanoarch.org/ IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH)], Boston, USA, 2015.
 
|}
 
|}
 
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| align=center width="70" |
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|- valign="top"
 
|- valign="top"
 
| '''authors''':
 
| '''authors''':
| Dan Alexandrescu, [[Mustafa Altun]], Lorena Anghel, Anna Bernasconi,<br> Valentina Ciriani, and Mehdi Tahoori
+
| width="450"| Dan Alexandrescu, [[Mustafa Altun]], Lorena Anghel, Anna Bernasconi, Valentina Ciriani, and Mehdi Tahoori
 
|- valign=top
 
|- valign=top
 
| '''presented&nbsp;at''':
 
| '''presented&nbsp;at''':
| [http://dsd-seaa2016.cs.ucy.ac.cy/index.php Euromicro Conference on Digital System Design (DSD)],<br> Limassol, Cyprus, 2016.
+
| width="450"| [http://dsd-seaa2016.cs.ucy.ac.cy/index.php Euromicro Conference on Digital System Design (DSD)], Limassol, Cyprus, 2016.
 
|}
 
|}
  
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|- valign="top"
 
|- valign="top"
 
| '''authors''':
 
| '''authors''':
| [[Mustafa Altun]] and [http://cadbio.com/wiki/index.php/Marc_Riedel Marc Riedel]
+
| [[Mustafa Altun]] and Marc Riedel
 
|- valign="top"
 
|- valign="top"
 
| '''appeared&nbsp;in''':
 
| '''appeared&nbsp;in''':
| [http://www.computer.org/portal/web/tc IEEE Transactions on Computers], <br>Vol. 61, Issue 11, pp. 1588&ndash;1600, 2012.
+
| width="450"| [http://www.computer.org/portal/web/tc IEEE Transactions on Computers], Vol. 61, Issue 11, pp. 1588&ndash;1600, 2012.
 
|- valign="top"
 
|- valign="top"
 
| '''presented&nbsp;at''':
 
| '''presented&nbsp;at''':
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|- valign="top"
 
|- valign="top"
 
| '''agency & program''':
 
| '''agency & program''':
| [http://ec.europa.eu/research/mariecurieactions/about-msca/actions/rise/index_en.htm European Union/European Commission H2020 MCSA <br> Research and Innovation Staff Exchange Program (RISE)]
+
| width="450"| [http://ec.europa.eu/research/mariecurieactions/about-msca/actions/rise/index_en.htm European Union/European Commission H2020 MSCA Research and Innovation Staff Exchange Program (RISE)]
 
|- valign="top"
 
|- valign="top"
 
| '''budget''':
 
| '''budget''':
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|- valign="top"
 
|- valign="top"
 
| '''budget''':
 
| '''budget''':
| 189.509 TL
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| 190.000 TL
 
|- valign="top"
 
|- valign="top"
 
| '''duration''':
 
| '''duration''':
| 2014-2017
+
| 2014-2017, ''completed''
 
|}
 
|}
 
|}
 
|}
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|-
 
|-
 
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| colspan="2" style="background:#8FBCBF; text-align:center; padding:1px; border-bottom:1px #8FBCBF solid;" |
<h2 style="margin:.1em; border-bottom:1px; font-size:140%; font-weight:bold;"> Reversible Circuit Design </h2>
+
<h2 style="margin:.1em; border-bottom:1px; font-size:140%; font-weight:bold;"> Reversible Circuit Design and CMOS Conversion </h2>
 
|-
 
|-
 
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| valign="top" style="padding:8px 8px 0px 8px; background:#f5fffa;" <!--H210 S4 V100--> |
  
Unlike conventional logic gates, reversible logic gates do not have “don’t-care” conditions. It means that an error occurring in any node of a reversible circuit is always seen at the output that gives a unique opportunity for error detecting/correcting. Motivated by this, we implement error tolerant reversible circuit blocks by exploiting parity preserving logic and Hamming codes.  We aim to design, fabricate, and test a fault-aware 8-bit reversible microprocessor for applications requiring high accuracy and reliability including aerospace, military, and medical applications.
+
Unlike conventional CMOS circuits, reversible circuits do not have latent faults, so faults occurring in internal circuit nodes
 +
always result in an error at the output. This is a unique feature for online or concurrent fault tolerance. Motivated by this, we implement error tolerant CMOS circuit blocks by exploiting reversible computing.  We first synthesize reversible circuits with reversible gates; then we make them fault-tolerant; and  finally we perform conversion from reversible gates to CMOS gates.
  
[[Image:Research-reversible-1.png|center|none|800px|link=]]
+
 
 +
[[Image:Research-reversible-2.png|center|none|800px|link=]]
 +
 
 +
<h3>
 +
 
 +
Synthesis </h3>
 +
 
 +
We propose a fast synthesis algorithm that implements any given reversible Boolean function with reversible gates. Instead of an exhaustive search on every given function, our algorithm creates a library of '''essential functions''' and performs '''sorting'''. As an example, to implement 4 bit circuits we only use 120 essential functions out of all 20922789888000 functions. We also perform optimization for both '''reversible and quantum circuit costs''' by considering adjacent gate pairs.
  
 
<h3>
 
<h3>
  
Synthesis and Optimization</h3>
+
Online Error Detection and Correction </h3>
  
We propose a fast synthesis algorithm that implements any given reversible Boolean function with quantum gates. Instead of an exhaustive search on every given function, our algorithm creates a library of '''essential functions''' and performs '''sorting'''. As an example, to implement 4 bit circuits we only use 120 essential functions out of all 20922789888000 functions. We also perform optimization for both '''reversible and quantum circuit costs''' by considering adjacent gate pairs.
+
We develop two techniques to make a reversible circuit fault-tolerant by using multiple-control Toffoli gates. The first technique is based on '''single parity preserving''', and offers error detection for odd number of errors at the output. The second technique is constructed on '''Hamming codes for error correction'''. We also claim that perfect error detection is possible with conservative reversible gates such as a Fredkin gate. As the next step, we '''utilize the proposed reversible circuits with conventional CMOS gates'''.
  
 
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|- valign=top
 
|- valign=top
 
| width="696" |'''Selected Publications'''
 
| width="696" |'''Selected Publications'''
 +
|}
 +
{| style="border:1px solid #abd5f5; background:#f1f5fc;"
 +
|
 +
{|
 +
|- valign=top
 +
| width="100" |'''title''':
 +
| width="524"|[[Media:Altun_Parvin_Cilasun_Exploiting_Reversible_Computing_for_CMOS_Fault_Tolerance.pdf| Exploiting Reversible Computing for Latent-Fault-Free Error Detecting/Correcting CMOS Circuits
 +
]]
 +
|- valign="top"
 +
| '''authors''':
 +
| [[Mustafa Altun]], Sajjad Parvin, and Husrev Cilasun
 +
|- valign="top"
 +
| '''appeared&nbsp;in''':
 +
| [http://ieeeaccess.ieee.org/ IEEE Access], , Vol. 6, pp. 74475&ndash;74484, 2018.
 +
|}
 +
| align=center width="70" |
 +
<span class="plainlinks">
 +
[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/7/7d/Altun_Parvin_Cilasun_Exploiting_Reversible_Computing_for_CMOS_Fault_Tolerance.pdf]]</span>
 +
<br>
 +
[[Media:Altun_Parvin_Cilasun_Exploiting_Reversible_Computing_for_CMOS_Fault_Tolerance.pdf | Paper]]
 
|}
 
|}
 
{| style="border:1px solid #abd5f5; background:#f1f5fc;"
 
{| style="border:1px solid #abd5f5; background:#f1f5fc;"
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| Omercan Susam and [[Mustafa Altun]]
 
| Omercan Susam and [[Mustafa Altun]]
 
|- valign="top"
 
|- valign="top"
| '''accepted&nbsp;in''':
+
| '''appeared&nbsp;in''':
| [http://www.oldcitypublishing.com/journals/mvlsc-home/ Journal of Multiple-Valued Logic and Soft Computing], 2016.
+
| width="450"| [http://www.oldcitypublishing.com/journals/mvlsc-home/ Journal of Multiple-Valued Logic and Soft Computing], Vol. 29, Issue 1-2, pp. 1&ndash;23, 2017.
 
|- valign="top"
 
|- valign="top"
 
| '''presented&nbsp;at''':
 
| '''presented&nbsp;at''':
| [http://www.ieee-icecs2014.org/ IEEE International Conference on Electronics Circuits and Systems<br> (ICECS)], Marseille, France, 2014.
+
| width="450"| [http://www.ieee-icecs2014.org/ IEEE International Conference on Electronics Circuits and Systems (ICECS)], Marseille, France, 2014.
 
|}
 
|}
 
| align=center width="70" |
 
| align=center width="70" |
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|- valign="top"
 
|- valign="top"
 
| '''duration''':
 
| '''duration''':
| 2016-2017
+
| 2016-2017, ''completed''
 
|}
 
|}
 
   
 
   
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|
 
|
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{| style="border:1px solid #abd5f5; background:#d0e5f5; padding:0.2em 0.5em; font-weight:bold;"
  
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|
 
|
 
{|
 
{|
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|- valign=top
 
|- valign=top
 
| '''presented&nbsp;at''':
 
| '''presented&nbsp;at''':
| [http://www.isvlsi.org/ IEEE Computer Society Annual Symposium on VLSI (ISVLSI)],<br> Pittsburgh, USA, 2016.
+
| width="450"| [http://www.isvlsi.org/ IEEE Computer Society Annual Symposium on VLSI (ISVLSI)], Pittsburgh, USA, 2016.
 
|}
 
|}
 
 
| align=center width="70" |
 
| align=center width="70" |
 
<span class="plainlinks">
 
<span class="plainlinks">
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</span>
 
</span>
 
<br> [http://www.ecc.itu.edu.tr/images/d/d6/Vahapoglu_Altun_Accurate_Synthesis_of_Arithmetic_Operations_with_Stochastic_Logic.pptx Poster]
 
<br> [http://www.ecc.itu.edu.tr/images/d/d6/Vahapoglu_Altun_Accurate_Synthesis_of_Arithmetic_Operations_with_Stochastic_Logic.pptx Poster]
 +
|}
 
|}
 
|}
  
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|- valign="top"
 
|- valign="top"
 
| '''budget''':
 
| '''budget''':
| 276.700 TL
+
| 260.000 TL
 
|- valign="top"
 
|- valign="top"
 
| '''duration''':
 
| '''duration''':
 
| 2017-2020
 
| 2017-2020
 
|}
 
|}
 +
|}
 +
 +
{| style="margin-left: auto; margin-right: 0px; border:1px solid #abd5f5; background:#f1f5fc;"
 +
 +
|
 +
{|
 +
|- valign=top
 +
| width="140" |'''title''':
 +
| width="558"| Gate and Transistor Implementations of Accurate Arithmetic Operation Blocks with Stochastic Logic
 +
|- valign="top"
 +
| '''agency & program''':
 +
| [http://bap.itu.edu.tr/ Istanbul Technical University Research Support Program (ITU-BAP)]
 +
|- valign="top"
 +
| '''duration''':
 +
| 2017-2019
 +
|}
 +
 +
|}
 +
 +
|}
 +
|}
 +
|}
 +
 +
 +
<!--        APPROXIMATE      -->
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 +
|-
 +
| colspan="2" style="background:#8FBC9F; text-align:center; padding:1px; border-bottom:1px #8FBCAF solid;" |
 +
<h2 style="margin:.1em; border-bottom:1px; font-size:140%; font-weight:bold;"> Approximate Circuit and System Design </h2>
 +
|-
 +
| valign="top" style="padding:8px 8px 0px 8px; background:#f5fffa;" <!--H210 S4 V100--> |
 +
 +
<h3>
 +
Power/Area Efficient Approximate System Design Methodology</h3>
 +
 +
This work provides '''power/area efficiency of circuit-level design with accuracy supervision of system-level design'''. The proposed
 +
method selects approximate computational units that minimize the total computation cost, yet maintaining
 +
the ultimate performance. The method investigates the overall system from the highest level down to the arithmetic units to determine the sufficient output quality at each block.
 +
 +
[[Image:Research-approximate.png|center|none|800px|link=]]
 +
 +
<!--        YAYIN      -->
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|
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{| style="border:1px solid #abd5f5; background:#d0e5f5; padding:0.2em 0.5em; font-weight:bold;"
 +
 +
|- valign=top
 +
| width="696" |'''Selected Publications'''
 +
|}
 +
{| style="border:1px solid #abd5f5; background:#f1f5fc;"
 +
|
 +
{|
 +
|- valign=top
 +
| width="100" |'''title''':
 +
| width="450"|[[Media:Ayhan_Altun_Circuit_Aware_Approximate_System_Design.pdf| Circuit Aware Approximate System Design with Case Studies in Image Processing and Neural Networks]]
 +
|- valign="top"
 +
| '''authors''':
 +
| Tuba Ayhan and [[Mustafa Altun]]
 +
|- valign="top"
 +
| '''appeared&nbsp;in''':
 +
| [http://ieeeaccess.ieee.org/ IEEE Access], Vol. 7, pp. 4726&ndash;4734, 2019.
 +
|- valign=top
 +
| '''presented&nbsp;at''':
 +
| width="450"| [http://www.isvlsi.org/ IEEE Computer Society Annual Symposium on VLSI (ISVLSI)], Bochum, Germany, 2017.
 +
|}
 +
 +
| align=center width="70" |
 +
<span class="plainlinks">
 +
[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/9/90/Ayhan_Altun_Circuit_Aware_Approximate_System_Design.pdf]]</span>
 +
<br>
 +
[[Media:Ayhan_Altun_Circuit_Aware_Approximate_System_Design.pdf | Paper]]
 +
| align="center" width="70" |
 +
<span class="plainlinks">
 +
 +
[[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/8/86/Ayhan_Kula_Altun_Approximate_System_Design_Methodology.pptx]]
 +
</span>
 +
<br> [http://www.ecc.itu.edu.tr/images/8/86/Ayhan_Kula_Altun_Approximate_System_Design_Methodology.pptx Slides]
 +
|}
 +
 +
|}
 +
 +
| style="border:1px solid transparent;" |
 +
<!--        PROJE      -->
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| class="MainPageBG" style="width:50%; border:0px solid #A9A9A9; vertical-align:top;"|
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{| style="margin-left: auto; margin-right: 0px; border:1px solid #abd5f5; background:#d0e5f5; padding:0.2em 0.5em; font-weight:bold;"
 +
 +
|- valign=top
 +
| width="696" |'''Funding Projects'''
 +
|}
 +
 +
{| style="margin-left: auto; margin-right: 0px; border:1px solid #abd5f5; background:#f1f5fc;"
 +
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|
 +
{|
 +
|- valign="top"
 +
| width="140" |'''title''':
 +
| width="558"|Design of Reconfigurable Circuits and Systems that can Perform Approximate Computation and their Use in Image Processing Applications Involving Learning
 +
|- valign="top"
 +
| '''agency & program''':
 +
| [http://www.tubitak.gov.tr/tr/destekler/akademik/ulusal-destek-programlari/icerik-1001-bilimsel-ve-teknolojik-arastirma-projelerini-destekleme-pr TUBITAK Scientific and Technological Research Projects Funding Program (1001)]
 +
|- valign="top"
 +
| '''budget''':
 +
| 230.000 TL
 +
|- valign="top"
 +
| '''duration''':
 +
| 2017-2020
 
|}
 
|}
 
|}
 
|}
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|-
 
|-
| colspan="2" style="background:#8FBC9F; text-align:center; padding:1px; border-bottom:1px #8FBC9F solid;" |
+
| colspan="2" style="background:#8FBC8F; text-align:center; padding:1px; border-bottom:1px #8FBC9F solid;" |
 
<h2 style="margin:.1em; border-bottom:1px; font-size:140%; font-weight:bold;"> Reliability of Electronic Products </h2>
 
<h2 style="margin:.1em; border-bottom:1px; font-size:140%; font-weight:bold;"> Reliability of Electronic Products </h2>
 
|-
 
|-
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| [[Mustafa Altun]] and Vehbi Comert
 
| [[Mustafa Altun]] and Vehbi Comert
 
|- valign=top
 
|- valign=top
| '''accepted&nbsp;in''':
+
| '''appeared&nbsp;in''':
| [http://www.journals.elsevier.com/reliability-engineering-and-system-safety Reliability Engineering and System Safety], 2016.
+
| width="450"| [http://www.journals.elsevier.com/reliability-engineering-and-system-safety Reliability Engineering and System Safety], Vol. 156, pp. 175&ndash;184, 2016.
 
|- valign=top
 
|- valign=top
 
| '''presented&nbsp;at''':
 
| '''presented&nbsp;at''':
| [http://rams.org/ Reliability and Maintainability Symposium (RAMS)],<br> Palm Harbor, USA, 2015.
+
| width="450"| [http://rams.org/ Reliability and Maintainability Symposium (RAMS)], Palm Harbor, USA, 2015.
 
|}
 
|}
  
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|- valign=top
 
|- valign=top
 
| width="100" |'''title''':
 
| width="100" |'''title''':
| width="450"|[[Media:Yadavari_EtAl_Effects_of_ZnO_Varistor_Degradation_on_the_Overvoltage_Protection_Mechanism_of_Electronic_Boards.pdf | Effects of ZnO Varistor Degradation on the Overvoltage Protection Mechanism of Electronic Boards]]
+
| width="450"|[[Media: Yadavari_Altun_Distinct_Degradation_Processes_in_ZnO_varistors.pdf | Distinct Degradation Processes in ZnO Varistors: Reliability Analysis and Modeling with Accelerated AC Tests]]
 
|- valign="top"
 
|- valign="top"
 
| '''authors''':
 
| '''authors''':
| Hadi Yadavari, Burak Sal, [[Mustafa Altun]], Ertunc Erturk, and Baris Ocak
+
| Hadi Yadavari and [[Mustafa Altun]]
 +
|- valign=top
 +
| '''appeared&nbsp;in''':
 +
| width="450"| [http://journals.tubitak.gov.tr/elektrik/index.htm;jsessionid=848207EBE52EFE10C78B78C76A0FEAD9 Turkish Journal of Electrical Engineering and Computer Sciences], Vol. 25, No. 4, pp. 3240&ndash;3252, 2017.
 
|- valign="top"
 
|- valign="top"
 
| '''presented&nbsp;at''':
 
| '''presented&nbsp;at''':
| [http://esrel2015.ethz.ch/ European Safety and Reliability Conference (ESREL)],<br> Zurich, Switzerland, 2015.
+
| width="450"| [http://esrel2015.ethz.ch/ European Safety and Reliability Conference (ESREL)], Zurich, Switzerland, 2015.
 
|}
 
|}
 
| align=center width="70" |
 
| align=center width="70" |
 
<span class="plainlinks">
 
<span class="plainlinks">
[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/d/d7/Yadavari_EtAl_Effects_of_ZnO_Varistor_Degradation_on_the_Overvoltage_Protection_Mechanism_of_Electronic_Boards.pdf]]</span>
+
[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/d/dd/Yadavari_Altun_Distinct_Degradation_Processes_in_ZnO_varistors.pdf]]</span>
 
<br>
 
<br>
[[Media:Yadavari_EtAl_Effects_of_ZnO_Varistor_Degradation_on_the_Overvoltage_Protection_Mechanism_of_Electronic_Boards.pdf | Paper]]
+
[[Media:Yadavari_Altun_Distinct_Degradation_Processes_in_ZnO_varistors.pdf | Paper]]
 
| align="center" width="70" |
 
| align="center" width="70" |
 
<span class="plainlinks">
 
<span class="plainlinks">
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|- valign="top"
 
|- valign="top"
 
| '''presented&nbsp;at''':
 
| '''presented&nbsp;at''':
| [http://esrel2015.ethz.ch/ European Safety and Reliability Conference (ESREL)],<br> Zurich, Switzerland, 2015.
+
| width="450"| [http://esrel2015.ethz.ch/ European Safety and Reliability Conference (ESREL)], Zurich, Switzerland, 2015.
 
|}
 
|}
 
| align=center width="70" |
 
| align=center width="70" |
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|- valign="top"
 
|- valign="top"
 
| '''budget''':
 
| '''budget''':
| 211.800 TL
+
| 210.000 TL
 
|- valign="top"
 
|- valign="top"
 
| '''duration''':
 
| '''duration''':
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|-
 
|-
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<h2 style="margin:.1em; border-bottom:1px; font-size:140%; font-weight:bold;"> Discrete Mathematics </h2>
 
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Revision as of 21:03, 28 January 2019

Our research aims to develop novel ways of computing, circuit design, and reliability for electronic circuits and systems. Our research mainly targets emerging technologies and new computing paradigms. Listed below are the research topics, ordered from newest to oldest as well as by considering their importance. Each topic is explained briefly in support with related papers and projects.

Contents

Computing with Nano-Crossbar Arrays

Nano-crossbar arrays have emerged as a strong candidate technology to replace CMOS in near future. They are regular and dense structures, and fabricated by exploiting self-assembly as opposed to purely using lithography based conventional and relatively costly CMOS fabrication techniques. Currently, nano-crossbar arrays are fabricated such that each crosspoint can be used as a conventional electronic component such as a diode, a FET, or a switch. This is a unique opportunity that allows us to integrate well developed conventional circuit design techniques into nano-crossbar arrays. Motivated by this, we aim to develop a complete synthesis and performance optimization methodology for switching nano-crossbar arrays that leads to the design and construction of an emerging nanocomputer.


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Synthesis

We study implementation of Boolean functions with nano-crossbar arrays where each crosspoint behaves as a diode, a FET, and a four-terminal switch. For these three types, we give array size formulations for a given Boolean function. Additionally, we focus on four-terminal switch based implementations and propose an algorithm that implements Boolean functions with optimal array sizes.

Fault Tolerance

We examine reconfigurable crossbar arrays by considering randomly occurred stuck-open and stuck-closed crosspoint faults. In the presence of permanent faults, a fast and accurate heuristic algorithm is proposed that uses the techniques of index sorting, backtracking, and row matching. In the presence of transient faults, tolerance analysis is performed by formally and recursively determining tolerable fault positions.

Selected Publications
title: Permanent and Transient Fault Tolerance for Reconfigurable Nano-Crossbar Arrays
authors: Onur Tunali and Mustafa Altun
appeared in: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 36, Issue 5, pp. 747–760, 2017.
presented at: IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH), Boston, USA, 2015.

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title: Synthesis and Performance Optimization of a Switching Nano-crossbar Computer
authors: Dan Alexandrescu, Mustafa Altun, Lorena Anghel, Anna Bernasconi, Valentina Ciriani, and Mehdi Tahoori
presented at: Euromicro Conference on Digital System Design (DSD), Limassol, Cyprus, 2016.

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title: Logic Synthesis for Switching Lattices
authors: Mustafa Altun and Marc Riedel
appeared in: IEEE Transactions on Computers, Vol. 61, Issue 11, pp. 1588–1600, 2012.
presented at: Design Automation Conference (DAC), Anaheim, USA, 2010.

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Funding Projects
title: Synthesis and Performance Optimization of a Switching Nano-Crossbar Computer
agency & program: European Union/European Commission H2020 MSCA Research and Innovation Staff Exchange Program (RISE)
budget: 724.500 EURO
duration: 2015-2019
title: Synthesis and Reliability Analysis of Nano Switching Arrays
agency & program: TUBITAK Career Program (3501)
budget: 190.000 TL
duration: 2014-2017, completed


Reversible Circuit Design and CMOS Conversion

Unlike conventional CMOS circuits, reversible circuits do not have latent faults, so faults occurring in internal circuit nodes always result in an error at the output. This is a unique feature for online or concurrent fault tolerance. Motivated by this, we implement error tolerant CMOS circuit blocks by exploiting reversible computing. We first synthesize reversible circuits with reversible gates; then we make them fault-tolerant; and finally we perform conversion from reversible gates to CMOS gates.


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Synthesis

We propose a fast synthesis algorithm that implements any given reversible Boolean function with reversible gates. Instead of an exhaustive search on every given function, our algorithm creates a library of essential functions and performs sorting. As an example, to implement 4 bit circuits we only use 120 essential functions out of all 20922789888000 functions. We also perform optimization for both reversible and quantum circuit costs by considering adjacent gate pairs.

Online Error Detection and Correction

We develop two techniques to make a reversible circuit fault-tolerant by using multiple-control Toffoli gates. The first technique is based on single parity preserving, and offers error detection for odd number of errors at the output. The second technique is constructed on Hamming codes for error correction. We also claim that perfect error detection is possible with conservative reversible gates such as a Fredkin gate. As the next step, we utilize the proposed reversible circuits with conventional CMOS gates.

Selected Publications
title: Exploiting Reversible Computing for Latent-Fault-Free Error Detecting/Correcting CMOS Circuits

authors: Mustafa Altun, Sajjad Parvin, and Husrev Cilasun
appeared in: IEEE Access, , Vol. 6, pp. 74475–74484, 2018.

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title: Fast Synthesis of Reversible Circuits using a Sorting Algorithm and Optimization
authors: Omercan Susam and Mustafa Altun
appeared in: Journal of Multiple-Valued Logic and Soft Computing, Vol. 29, Issue 1-2, pp. 1–23, 2017.
presented at: IEEE International Conference on Electronics Circuits and Systems (ICECS), Marseille, France, 2014.

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Funding Projects
title: Implementation of a Fault-Aware 8-Bit Reversible Microprocessor
agency & program: TUBITAK Short Term R&D Funding Program (1002)
budget: 30.000 TL
duration: 2016-2017, completed
title: Quantum Circuit Design and Computation
agency & program: Istanbul Technical University Research Support Program (ITU-BAP)
duration: 2014-2015, completed


Stochastic Circuit Design

Accurate Arithmetic Implementations

We propose a method to overcome the main drawback in stochastic computing, low accuracy or related long computing times. Our method manipulates stochastic bit streams with the aid of feedback mechanisms. We implement error-free arithmetic multiplier and adder circuits by considering performance parameters area, delay, and accuracy.

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Selected Publications
title: Accurate Synthesis of Arithmetic Operations with Stochastic Logic
authors: Ensar Vahapoglu and Mustafa Altun
presented at: IEEE Computer Society Annual Symposium on VLSI (ISVLSI), Pittsburgh, USA, 2016.

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Poster

Funding Projects
title: Implementation of Accurate Stochastic Circuit Blocks and their Applications for Printed/Flexible Electronic Systems
agency & program: TUBITAK Scientific and Technological Research Projects Funding Program (1001)
budget: 260.000 TL
duration: 2017-2020
title: Gate and Transistor Implementations of Accurate Arithmetic Operation Blocks with Stochastic Logic
agency & program: Istanbul Technical University Research Support Program (ITU-BAP)
duration: 2017-2019


Approximate Circuit and System Design

Power/Area Efficient Approximate System Design Methodology

This work provides power/area efficiency of circuit-level design with accuracy supervision of system-level design. The proposed method selects approximate computational units that minimize the total computation cost, yet maintaining the ultimate performance. The method investigates the overall system from the highest level down to the arithmetic units to determine the sufficient output quality at each block.

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Selected Publications
title: Circuit Aware Approximate System Design with Case Studies in Image Processing and Neural Networks
authors: Tuba Ayhan and Mustafa Altun
appeared in: IEEE Access, Vol. 7, pp. 4726–4734, 2019.
presented at: IEEE Computer Society Annual Symposium on VLSI (ISVLSI), Bochum, Germany, 2017.

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Funding Projects
title: Design of Reconfigurable Circuits and Systems that can Perform Approximate Computation and their Use in Image Processing Applications Involving Learning
agency & program: TUBITAK Scientific and Technological Research Projects Funding Program (1001)
budget: 230.000 TL
duration: 2017-2020


Reliability of Electronic Products

The rapid developments in electronics, especially in the last decade, have elevated the importance of electronics reliability. Conventionally used accelerated reliability tests have lost their significance; time consuming and expensive feature of these tests is against the demands of today's very rapid electronic product cycles. In this study, we propose less costly, yet accurate, reliability prediction techniques using field return data, new accelerated test methodologies, and physics of failure based simulations. We cooperate with one of the Europe’s largest household appliance companies Arçelik A.Ş..

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Reliability Analysis and Prediction with Field Data

We propose an accurate reliability prediction model for high-volume electronic products throughout their warranty periods by using field return data. Our model is constructed on a Weibull-exponential hazard rate scheme by using the proposed change point detection method based on backward and forward data analysis. Our prediction model can make a 36-month (full warranty) reliability prediction of an electronic board with using its field data as short as 3 months.

Degradation Processes in Varistors

We investigate different degradation mechanisms of ZnO varistors. We propose a model showing how the varistor voltage Vv changes by time for different stress levels. For this purpose, accelerated degradation tests are applied for different AC current levels; then voltage values are measured. Different from the common practice in the literature that considers a degradation with only decreasing Vv values, we demonstrate either an increasing or a decreasing trend in the Vv parameter.

Calibrated Accelerated Life Testing

Dramatic decrease in failure rates for electronic products makes conventional accelerated life tests (ALT) extremely time consuming and costly. Recently proposed calibrated accelerated life tests (CALT) aim to use fewer samples than those used in ALT. We thoroughly compare ALT and CALT by considering the effects of failure rate, acceleration factor, and stress level on the required test time.

Selected Publications
title: A Change-Point based Reliability Prediction Model using Field Return Data
authors: Mustafa Altun and Vehbi Comert
appeared in: Reliability Engineering and System Safety, Vol. 156, pp. 175–184, 2016.
presented at: Reliability and Maintainability Symposium (RAMS), Palm Harbor, USA, 2015.

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title: Distinct Degradation Processes in ZnO Varistors: Reliability Analysis and Modeling with Accelerated AC Tests
authors: Hadi Yadavari and Mustafa Altun
appeared in: Turkish Journal of Electrical Engineering and Computer Sciences, Vol. 25, No. 4, pp. 3240–3252, 2017.
presented at: European Safety and Reliability Conference (ESREL), Zurich, Switzerland, 2015.

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title: Extensive Investigation of Calibrated Accelerated Life Testing (CALT) in Comparison with Classical Accelerated Life Testing (ALT)
authors: Burak Sal and Mustafa Altun
presented at: European Safety and Reliability Conference (ESREL), Zurich, Switzerland, 2015.

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Funding Projects
title: An Accurate Reliability Methodology for Appliance Electronic Cards
agency & program: TUBITAK University-Industry Collaboration Grant Program (1505)
budget: 210.000 TL
duration: 2013-2015, completed
title: Gate Oxide Breakdown Failure Mechanism of CMOS Transistors
agency & program: TUBITAK Industry Oriented Senior Project Support Program (2241/A)
duration: 2013-2014, completed


Analog Circuit Design

Positive Feedback

The conventional wisdom is that analog circuits should not include positive feedback loops. As controversial as it seems, we have successfully used positive feedback for impedance improvement in a current amplifier. With adding few transistors we have achieved very low input resistance values. Additionally, we have proposed a new fully-differential current amplifier and tested it in a filter application.

Selected Publications
title: Design of a Fully Differential Current Mode Operational Amplifier with its Filter Applications
authors: Mustafa Altun and Hakan Kuntman
appeared in: AEU International Journal of Electronics and Communications, Vol. 62, Issue 3, pp. 39–44, 2008.
presented at: ACM Great Lakes Symposium on VLSI (GLSVLSI), Stresa, Italy, 2007.

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Discrete Mathematics

Self Duality Problem

The problem of testing whether a monotone Boolean function in irredundant disjuntive normal form (IDNF) is self-dual is one of few problems in circuit/time complexity whose precise tractability status is unknown. We have focused on this famous problem. We have shown that monotone self-dual Boolean functions in IDNF do not have more variables than disjuncts. We have proposed an algorithm to test whether a monotone Boolean function in IDNF with n variables and n disjuncts is self-dual. The algorithm runs in O(n^3) time.

Selected Publications
title: A Study on Monotone Self-dual Boolean Functions
authors: Mustafa Altun and Marc Riedel
appeared  in: Acta Mathematicae Applicatae Sinica - English Series, Vol. 33, Issue 1, pp. 43–52, 2017.

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