Publications and Presentations
From The Emerging Circuits and Computation Group at ITU
(Difference between revisions)
(→Approximate Computing) |
(→Logic Synthesis) |
||
(22 intermediate revisions by one user not shown) | |||
Line 27: | Line 27: | ||
<span class="plainlinks"> | <span class="plainlinks"> | ||
− | [[File:PPT.jpg|60px|link=]] | + | [[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/7/71/Safaltin_EtAl_Technology_Development_for_Switching_Lattices.pptx]] |
</span> | </span> | ||
− | <br> | + | <br> [http://www.ecc.itu.edu.tr/images/7/71/Safaltin_EtAl_Technology_Development_for_Switching_Lattices.pptx Slides] |
− | Slides | + | |
|} | |} | ||
Line 224: | Line 223: | ||
| Furkan Peker and [[Mustafa Altun]] | | Furkan Peker and [[Mustafa Altun]] | ||
|- valign="top" | |- valign="top" | ||
− | | ''' | + | | '''appeared in''': |
− | | width="624" | [http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=6687315 IEEE Transactions on Multi-Scale Computing Systems], | + | | width="624" | [http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=6687315 IEEE Transactions on Multi-Scale Computing Systems], Vol. 4, No. 4, pp. 522–532, 2018. |
|} | |} | ||
| align=center width="70" | | | align=center width="70" | | ||
Line 397: | Line 396: | ||
=== Logic Synthesis === | === Logic Synthesis === | ||
+ | |||
+ | {| style="border:2px solid #abd5f5; background:#f1f5fc;" | ||
+ | | | ||
+ | {| | ||
+ | |- valign=top | ||
+ | | width="100" |'''title''': | ||
+ | | width="624"|[[Media:Aksoy_Altun_Realizations_with_Switching_Lattices.pdf | Novel Methods for Efficient Realization of Logic Functions Using Switching Lattices]] | ||
+ | |- valign="top" | ||
+ | | '''authors''': | ||
+ | | Levent Aksoy and [[Mustafa Altun]] | ||
+ | |- valign="top" | ||
+ | | '''accepted in''': | ||
+ | | [http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12 IEEE Transactions on Computers], 2019. | ||
+ | |} | ||
+ | | align=center width="70" | | ||
+ | <span class="plainlinks"> | ||
+ | [[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/e/e0/Aksoy_Altun_Realizations_with_Switching_Lattices.pdf]]</span> | ||
+ | <br> | ||
+ | [[Media:Aksoy_Altun_Realizations_with_Switching_Lattices.pdf | Paper]] | ||
+ | |} | ||
{| style="border:2px solid #abd5f5; background:#f1f5fc;" | {| style="border:2px solid #abd5f5; background:#f1f5fc;" | ||
Line 420: | Line 439: | ||
<span class="plainlinks"> | <span class="plainlinks"> | ||
− | [[File:PPT.jpg|60px|link=]] | + | [[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/5/54/Aksoy_Altun_SAT_based_Synthesis_of_Switching_Lattices.pptx]] |
</span> | </span> | ||
− | <br> | + | <br> [http://www.ecc.itu.edu.tr/images/5/54/Aksoy_Altun_SAT_based_Synthesis_of_Switching_Lattices.pptx Slides] |
− | Slides | + | |
|} | |} | ||
Line 485: | Line 503: | ||
|- valign="top" | |- valign="top" | ||
| '''appeared in''': | | '''appeared in''': | ||
− | | [http:// | + | | [http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12 IEEE Transactions on Computers], Vol. 61, Issue 11, pp. 1588–1600, 2012. |
<!-- |- valign="top" | <!-- |- valign="top" | ||
| '''presented at''': | | '''presented at''': | ||
Line 558: | Line 576: | ||
|} | |} | ||
− | == Reversible | + | == Reversible Computing == |
+ | |||
+ | === CMOS Fault Tolerance === | ||
+ | |||
+ | {| style="border:2px solid #abd5f5; background:#f1f5fc;" | ||
+ | |||
+ | | | ||
+ | {| | ||
+ | |- valign=top | ||
+ | | width="100" |'''title''': | ||
+ | | width="550"|[[Media:Parvin_Altun_CMOS_Fault_Tolerance_with_Preservative_Reversible_Gates.pdf | Implementation of CMOS Logic Circuits with Perfect Fault Detection Using Preservative Reversible Gates]] | ||
+ | |- valign="top" | ||
+ | | '''authors''': | ||
+ | | Sajjad Parvin and [[Mustafa Altun]] | ||
+ | |- valign=top | ||
+ | | '''presented at''': | ||
+ | | width="550"| [http://tima.univ-grenoble-alpes.fr/conferences/iolts/iolts19/ IEEE International Symposium on On-Line Testing and Robust System Design (IOLTS)], Rhodes Island, Greece, 2019. | ||
+ | |} | ||
+ | |||
+ | | align=center width="70" | | ||
+ | <span class="plainlinks"> | ||
+ | [[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/e/ee/Parvin_Altun_CMOS_Fault_Tolerance_with_Preservative_Reversible_Gates.pdf]]</span> | ||
+ | <br> | ||
+ | [[Media:Parvin_Altun_CMOS_Fault_Tolerance_with_Preservative_Reversible_Gates.pdf | Paper]] | ||
+ | | align="center" width="70" | | ||
+ | <span class="plainlinks"> | ||
+ | |||
+ | [[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/f/f4/Parvin_Altun_CMOS_Fault_Tolerance_with_Preservative_Reversible_Gates.pptx]] | ||
+ | </span> | ||
+ | <br> [http://www.ecc.itu.edu.tr/images/f/f4/Parvin_Altun_CMOS_Fault_Tolerance_with_Preservative_Reversible_Gates.pptx Poster] | ||
+ | |} | ||
{| style="border:2px solid #abd5f5; background:#f1f5fc; " | {| style="border:2px solid #abd5f5; background:#f1f5fc; " | ||
Line 572: | Line 620: | ||
| [[Mustafa Altun]], Sajjad Parvin, and Husrev Cilasun | | [[Mustafa Altun]], Sajjad Parvin, and Husrev Cilasun | ||
|- valign="top" | |- valign="top" | ||
− | | ''' | + | | '''appeared in''': |
− | | [http://ieeeaccess.ieee.org/ IEEE Access], 2018. | + | | [http://ieeeaccess.ieee.org/ IEEE Access], Vol. 6, pp. 74475–74484, 2018. |
|} | |} | ||
| align=center width="70" | | | align=center width="70" | | ||
Line 605: | Line 653: | ||
|} | |} | ||
+ | |||
+ | === Logic Synthesis === | ||
{| style="border:2px solid #abd5f5; background:#f1f5fc; " | {| style="border:2px solid #abd5f5; background:#f1f5fc; " | ||
Line 800: | Line 850: | ||
== Approximate Computing == | == Approximate Computing == | ||
+ | |||
+ | {| style="border:2px solid #abd5f5; background:#f1f5fc;" | ||
+ | | | ||
+ | {| | ||
+ | |- valign=top | ||
+ | | width="100" |'''title''': | ||
+ | | width="624"|[[Media:Nojehdeh_Altun_Approximate_Adders_Multipliers.pdf | Systematic Synthesis of Approximate Adders and Multipliers with Accurate Error Calculations]] | ||
+ | |- valign="top" | ||
+ | | '''authors''': | ||
+ | | Mohammadreza Nojehdeh and [[Mustafa Altun]] | ||
+ | |- valign="top" | ||
+ | | '''accepted in''': | ||
+ | | width="624" | [http://www.journals.elsevier.com/integration Integration, the VLSI Journal], 2019. | ||
+ | |} | ||
+ | | align=center width="70" | | ||
+ | <span class="plainlinks"> | ||
+ | [[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/c/c8/Nojehdeh_Altun_Approximate_Adders_Multipliers.pdf]]</span> | ||
+ | <br> | ||
+ | [[Media:Nojehdeh_Altun_Approximate_Adders_Multipliers.pdf | Paper]] | ||
+ | |} | ||
{| style="border:2px solid #abd5f5; background:#f1f5fc; " | {| style="border:2px solid #abd5f5; background:#f1f5fc; " | ||
Line 895: | Line 965: | ||
|- valign="top" | |- valign="top" | ||
| '''presented at''': | | '''presented at''': | ||
− | | width="550"| [http:// | + | | width="550"| [http://ieeexplore.ieee.org/xpl/conhome.jsp?punumber=1001786 Sinyal İşleme ve İletişim Uygulamaları Kurultayı (SİU)], Izmir, Turkey, 2018. |
|} | |} | ||
Line 914: | Line 984: | ||
== Large-Area Electronics == | == Large-Area Electronics == | ||
+ | |||
+ | === Transistor Fabrication === | ||
+ | |||
+ | {| style="border:2px solid #abd5f5; background:#f1f5fc;" | ||
+ | |||
+ | | | ||
+ | {| | ||
+ | |- valign=top | ||
+ | | width="100" |'''title''': | ||
+ | | width="550"|[[Media:Yedikardes_EtAl_P3HT_WO3_Organic_Transistors.pdf | The Enhanced Electronic Properties of P3HT-WO3 Hybrid Thin Film Transistors]] | ||
+ | |- valign="top" | ||
+ | | '''authors''': | ||
+ | | width="550"|Beyza Yedikardes, Fereshteh Ordokhani, Nihat Akkan, Ece Kurt, Esra Zayim, Nilgün Yavuz, and [[Mustafa Altun]] | ||
+ | |- valign=top | ||
+ | | '''presented at''': | ||
+ | | width="550"| [http://www.advanced-nanomaterials-conference.com/ International Conference on Advanced Nanomaterials (ANM)], Aveiro, Portugal, 2019. | ||
+ | |} | ||
+ | |||
+ | | align=center width="70" | | ||
+ | <span class="plainlinks"> | ||
+ | [[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/d/d5/Yedikardes_EtAl_P3HT_WO3_Organic_Transistors.pdf]]</span> | ||
+ | <br> | ||
+ | [[Media:Yedikardes_EtAl_P3HT_WO3_Organic_Transistors.pdf | Abstract]] | ||
+ | | align="center" width="70" | | ||
+ | <span class="plainlinks"> | ||
+ | |||
+ | [[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/2/25/Yedikardes_EtAl_P3HT_WO3_Organic_Transistors.pptx]] | ||
+ | </span> | ||
+ | <br> [http://www.ecc.itu.edu.tr/images/2/25/Yedikardes_EtAl_P3HT_WO3_Organic_Transistors.pptx Slides] | ||
+ | |} | ||
=== Organic Transistor Modeling === | === Organic Transistor Modeling === |
Revision as of 09:44, 18 October 2019
Listed below are the papers, first authored by our group members as an indication that the related research is mainly conducted in our group, and the presentations. Research topics are ordered from newest to oldest as well as by considering their importance. Under each topic, papers are ordered from newest to oldest. All materials are subject to copyrights.
Contents |
Computing with Nano-Crossbar Arrays
Technology Development
|
|
Comprehensive Performance Optimization
|
|
|
|
|
|
|
|
|
|
|
Fault/Defect/Variation Tolerance
|
|
|
|
|
|
|
|
|
|
|
|
Logic Synthesis
|
|
|
|
|
|
|
|
|
National Publications in Turkish
|
|
|
Reversible Computing
CMOS Fault Tolerance
|
|
|
|
Logic Synthesis
|
|
|
National Publications in Turkish
|
|
|
Stochastic and Bit Stream Computing
|
|
|
|
|
National Publications in Turkish
|
|
|
Approximate Computing
|
|
|
|
|
|
National Publications in Turkish
|
|
|
Large-Area Electronics
Transistor Fabrication
|
|
Organic Transistor Modeling
|
|
Reliability of Electronic Products
|
|
|
|
|
|
|
|
|
|
National Publications in Turkish
|
|
|
Analog Circuit Design
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
National Publications in Turkish
|
|
Discrete Mathematics
|
|