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− | [[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/b/bd/Safaltin_EtAl_Technology_Development_for_Switching_Lattices.pptx]] | + | [[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/7/71/Safaltin_EtAl_Technology_Development_for_Switching_Lattices.pptx]] |
| </span> | | </span> |
| <br> [http://www.ecc.itu.edu.tr/images/7/71/Safaltin_EtAl_Technology_Development_for_Switching_Lattices.pptx Slides] | | <br> [http://www.ecc.itu.edu.tr/images/7/71/Safaltin_EtAl_Technology_Development_for_Switching_Lattices.pptx Slides] |
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− | [[File:PPT.jpg|60px|link=]] | + | [[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/5/54/Aksoy_Altun_SAT_based_Synthesis_of_Switching_Lattices.pptx]] |
| </span> | | </span> |
− | <br> | + | <br> [http://www.ecc.itu.edu.tr/images/5/54/Aksoy_Altun_SAT_based_Synthesis_of_Switching_Lattices.pptx Slides] |
− | Slides | + | |
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− | == Reversible Circuit Design == | + | == Reversible Computing == |
| + | |
| + | === CMOS Fault Tolerance === |
| + | |
| + | {| style="border:2px solid #abd5f5; background:#f1f5fc;" |
| + | |
| + | | |
| + | {| |
| + | |- valign=top |
| + | | width="100" |'''title''': |
| + | | width="550"|[[Media:Parvin_Altun_CMOS_Fault_Tolerance_with_Preservative_Reversible_Gates.pdf | Implementation of CMOS Logic Circuits with Perfect Fault Detection Using Preservative Reversible Gates]] |
| + | |- valign="top" |
| + | | '''authors''': |
| + | | Sajjad Parvin and [[Mustafa Altun]] |
| + | |- valign=top |
| + | | '''presented at''': |
| + | | width="550"| [http://tima.univ-grenoble-alpes.fr/conferences/iolts/iolts19/ IEEE International Symposium on On-Line Testing and Robust System Design (IOLTS)], Rhodes Island, Greece, 2019. |
| + | |} |
| + | |
| + | | align=center width="70" | |
| + | <span class="plainlinks"> |
| + | [[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/e/ee/Parvin_Altun_CMOS_Fault_Tolerance_with_Preservative_Reversible_Gates.pdf]]</span> |
| + | <br> |
| + | [[Media:Parvin_Altun_CMOS_Fault_Tolerance_with_Preservative_Reversible_Gates.pdf | Paper]] |
| + | | align="center" width="70" | |
| + | <span class="plainlinks"> |
| + | |
| + | [[File:PPT.jpg|60px|link=]] |
| + | </span> |
| + | <br> Poster |
| + | |} |
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| {| style="border:2px solid #abd5f5; background:#f1f5fc; " | | {| style="border:2px solid #abd5f5; background:#f1f5fc; " |
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| |} | | |} |
| + | |
| + | === Logic Synthesis === |
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| {| style="border:2px solid #abd5f5; background:#f1f5fc; " | | {| style="border:2px solid #abd5f5; background:#f1f5fc; " |