Publications and Presentations
From The Emerging Circuits and Computation Group at ITU
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− | Listed below are the papers, '''first authored''' by our group members as an indication that the related research is mainly conducted in our group, and the presentations. All materials are subject to copyrights. | + | Listed below are the papers, '''first authored''' by our group members as an indication that the related research is mainly conducted in our group, and the presentations. Research topics are ordered from newest to oldest as well as by considering their importance. Under each topic, papers are ordered from newest to oldest. All materials are subject to copyrights. |
<div style="float:center; font-size:110%; font-weight:bold; clear:both; padding:0; margin:0.0em;">__TOC__</div> | <div style="float:center; font-size:110%; font-weight:bold; clear:both; padding:0; margin:0.0em;">__TOC__</div> | ||
== Computing with Nano-Crossbar Arrays == | == Computing with Nano-Crossbar Arrays == | ||
+ | |||
+ | === Technology Development === | ||
{| style="border:2px solid #abd5f5; background:#f1f5fc;" | {| style="border:2px solid #abd5f5; background:#f1f5fc;" | ||
+ | |||
| | | | ||
− | {| | + | {| |
|- valign=top | |- valign=top | ||
| width="100" |'''title''': | | width="100" |'''title''': | ||
− | | width="550"|[[Media: | + | | width="550"|[[Media: Safaltin_EtAl_Technology_Development_for_Switching_Lattices.pdf| Realization of Four-Terminal Switching Lattices: Technology Development and Circuit Modeling]] |
|- valign="top" | |- valign="top" | ||
| '''authors''': | | '''authors''': | ||
− | | Ceylan Morgul, | + | | width="550"| Serzat Safaltin, Oguz Gencer, Ceylan Morgul, Levent Aksoy, Sebahattin Gurmen, Csaba Andras Moritz, and [[Mustafa Altun]] |
|- valign="top" | |- valign="top" | ||
| '''presented at''': | | '''presented at''': | ||
− | | width="550"|[http://www. | + | | width="550"| [http://www.date-conference.com/ Design, Automation and Test in Europe (DATE)], Florence, Italy, 2019. |
|} | |} | ||
− | | align=center width="70" | | + | | align=center width="70" | |
<span class="plainlinks"> | <span class="plainlinks"> | ||
− | [[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/ | + | [[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/2/2c/Safaltin_EtAl_Technology_Development_for_Switching_Lattices.pdf]]</span> |
<br> | <br> | ||
− | [[Media: | + | [[Media:Safaltin_EtAl_Technology_Development_for_Switching_Lattices.pdf | Paper]] |
− | | align="center" width="70" | | + | | align="center" width="70" | |
<span class="plainlinks"> | <span class="plainlinks"> | ||
[[File:PPT.jpg|60px|link=]] | [[File:PPT.jpg|60px|link=]] | ||
</span> | </span> | ||
− | <br> Slides | + | <br> |
+ | Slides | ||
|} | |} | ||
+ | |||
+ | === Comprehensive Performance Optimization=== | ||
{| style="border:2px solid #abd5f5; background:#f1f5fc;" | {| style="border:2px solid #abd5f5; background:#f1f5fc;" | ||
Line 34: | Line 40: | ||
|- valign=top | |- valign=top | ||
| width="100" |'''title''': | | width="100" |'''title''': | ||
− | | width=" | + | | width="550"|[[Media: Morgul_EtAl_Integrated_Synthesis_Methodology for_Crossbar_Arrays.pdf | Integrated Synthesis Methodology for Crossbar Arrays]] |
|- valign="top" | |- valign="top" | ||
| '''authors''': | | '''authors''': | ||
− | | | + | | width="550"| Ceylan Morgul, Luca Frontini, Onur Tunali, Ioana Vatajelu, Valentina Ciriani, Lorena Anghel, Csaba Moritz, Mircea Stan, Dan Alexandrescu, and [[Mustafa Altun]] |
|- valign="top" | |- valign="top" | ||
− | | ''' | + | | '''presented at''': |
− | | width=" | + | | width="550"|[http://www.nanoarch.org/ IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH)], Athens, Greece, 2018. |
|} | |} | ||
| align=center width="70" | | | align=center width="70" | | ||
<span class="plainlinks"> | <span class="plainlinks"> | ||
− | [[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/ | + | [[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/b/b1/Morgul_EtAl_Integrated_Synthesis_Methodology_for_Crossbar_Arrays.pdf]]</span> |
<br> | <br> | ||
− | [[Media: | + | [[Media:Morgul_EtAl_Integrated_Synthesis_Methodology for_Crossbar_Arrays.pdf | Paper]] |
+ | | align="center" width="70" | | ||
+ | <span class="plainlinks"> | ||
+ | |||
+ | [[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/b/bd/Morgul_EtAl_Integrated_Synthesis_Methodology_for_Crossbar_Arrays.pptx]] | ||
+ | </span> | ||
+ | <br> [http://www.ecc.itu.edu.tr/images/b/bd/Morgul_EtAl_Integrated_Synthesis_Methodology_for_Crossbar_Arrays.pptx Slides] | ||
|} | |} | ||
Line 60: | Line 72: | ||
| Onur Tunali and [[Mustafa Altun]] | | Onur Tunali and [[Mustafa Altun]] | ||
|- valign="top" | |- valign="top" | ||
− | | ''' | + | | '''presented at''': |
| width="550"| [http://www.date-conference.com/ Design, Automation and Test in Europe (DATE)], Dresden, Germany, 2018. | | width="550"| [http://www.date-conference.com/ Design, Automation and Test in Europe (DATE)], Dresden, Germany, 2018. | ||
|} | |} | ||
Line 74: | Line 86: | ||
</span> | </span> | ||
<br> [http://www.ecc.itu.edu.tr/images/b/b8/Tunali_Altun_Logic_Synthesis_and_Defect_Tolerance_for_Memristive_Crossbars.pptx Slides] | <br> [http://www.ecc.itu.edu.tr/images/b/b8/Tunali_Altun_Logic_Synthesis_and_Defect_Tolerance_for_Memristive_Crossbars.pptx Slides] | ||
+ | |} | ||
+ | |||
+ | {| style="border:2px solid #abd5f5; background:#f1f5fc;" | ||
+ | |||
+ | | | ||
+ | {| | ||
+ | |- valign=top | ||
+ | | width="100" |'''title''': | ||
+ | | width="550"|[[Media:Altun_EtAl_Synthesis_and_Testing_for_Switching_Nano_Crossbar_Arrays.pdf | Logic Synthesis and Testing Techniques for Switching Nano-Crossbar Arrays]] | ||
+ | |- valign="top" | ||
+ | | '''authors''': | ||
+ | | width="550"| Dan Alexandrescu, [[Mustafa Altun]], Lorena Anghel, Anna Bernasconi, Valentina Ciriani, Luca Frontini, and Mehdi Tahoori | ||
+ | |- valign=top | ||
+ | | '''appeared in''': | ||
+ | | width="624" | [http://www.journals.elsevier.com/microprocessors-and-microsystems/ Microprocessors and Microsystems], Vol. 54, pp. 14–25, 2017. | ||
+ | |} | ||
+ | | align=center width="70" | | ||
+ | <span class="plainlinks"> | ||
+ | [[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/0/0a/Altun_EtAl_Synthesis_and_Testing_for_Switching_Nano_Crossbar_Arrays.pdf]]</span> | ||
+ | <br> | ||
+ | [[Media:Altun_EtAl_Synthesis_and_Testing_for_Switching_Nano_Crossbar_Arrays.pdf | Paper]] | ||
+ | |||
+ | |} | ||
+ | |||
+ | {| style="border:2px solid #abd5f5; background:#f1f5fc;" | ||
+ | | | ||
+ | {| | ||
+ | |- valign=top | ||
+ | | width="100" |'''title''': | ||
+ | | width="550"|[[Media:Altun_Ciriani_Tahoori_Computing_with_Nano-Crossbar_Arrays.pdf | Computing with Nano-Crossbar Arrays: Logic Synthesis and Fault Tolerance]] | ||
+ | |- valign="top" | ||
+ | | '''authors''': | ||
+ | | [[Mustafa Altun]], Valentina Ciriani, and Mehdi Tahoori | ||
+ | |- valign="top" | ||
+ | | '''presented at''': | ||
+ | | [http://www.date-conference.com/ Design, Automation and Test in Europe (DATE)], Lausanne, Switzerland, 2017. | ||
+ | |} | ||
+ | | align=center width="70" | | ||
+ | <span class="plainlinks"> | ||
+ | [[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/0/09/Altun_Ciriani_Tahoori_Computing_with_Nano-Crossbar_Arrays.pdf]]</span> | ||
+ | <br> | ||
+ | [[Media:Altun_Ciriani_Tahoori_Computing_with_Nano-Crossbar_Arrays.pdf | Paper]] | ||
+ | | align="center" width="70" | | ||
+ | <span class="plainlinks"> | ||
+ | |||
+ | [[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/2/28/Altun_Ciriani_Tahoori_Computing_with_Nano-Crossbar_Arrays.pptx]] | ||
+ | </span> | ||
+ | <br> [http://www.ecc.itu.edu.tr/images/2/28/Altun_Ciriani_Tahoori_Computing_with_Nano-Crossbar_Arrays.pptx Slides] | ||
+ | |} | ||
+ | |||
+ | {| style="border:2px solid #abd5f5; background:#f1f5fc;" | ||
+ | |||
+ | | | ||
+ | {| | ||
+ | |- valign=top | ||
+ | | width="100" |'''title''': | ||
+ | | width="550"|[[Media:Altun_EtAl_Synthesis_and_Performance_Optimization_of_a_Switching_Nano-crossbar_Computer.pdf | Synthesis and Performance Optimization of a Switching Nano-crossbar Computer]] | ||
+ | |- valign="top" | ||
+ | | '''authors''': | ||
+ | | width="550"| Dan Alexandrescu, [[Mustafa Altun]], Lorena Anghel, Anna Bernasconi, Valentina Ciriani, and Mehdi Tahoori | ||
+ | |- valign=top | ||
+ | | '''presented at''': | ||
+ | | [http://dsd-seaa2016.cs.ucy.ac.cy/index.php Euromicro Conference on Digital System Design (DSD)], Limassol, Cyprus, 2016. | ||
+ | |} | ||
+ | |||
+ | | align=center width="70" | | ||
+ | <span class="plainlinks"> | ||
+ | [[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/a/ab/Altun_EtAl_Synthesis_and_Performance_Optimization_of_a_Switching_Nano-crossbar_Computer.pdf]]</span> | ||
+ | <br> | ||
+ | [[Media:Altun_EtAl_Synthesis_and_Performance_Optimization_of_a_Switching_Nano-crossbar_Computer.pdf | Paper]] | ||
+ | | align="center" width="70" | | ||
+ | <span class="plainlinks"> | ||
+ | |||
+ | [[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/7/7f/Altun_EtAl_Synthesis_and_Performance_Optimization_of_a_Switching_Nano-crossbar_Computer_SLIDES.pdf]] | ||
+ | </span> | ||
+ | <br> [[Media:Altun_EtAl_Synthesis_and_Performance_Optimization_of_a_Switching_Nano-crossbar_Computer_SLIDES.pdf | Slides]] | ||
+ | |} | ||
+ | |||
+ | {| style="border:2px solid #abd5f5; background:#f1f5fc;" | ||
+ | |||
+ | | | ||
+ | {| | ||
+ | |- valign=top | ||
+ | | width="100" |'''title''': | ||
+ | | width="550"|[[Media:Morgul_Peker_Altun_Power-Delay-Area_Performance_Modeling_and_Analysis_for_Nano-Crossbar_Arrays.pdf | Power-Delay-Area Performance Modeling and Analysis for Nano-Crossbar Arrays]] | ||
+ | |- valign="top" | ||
+ | | '''authors''': | ||
+ | | Ceylan Morgul, Furkan Peker, and [[Mustafa Altun]] | ||
+ | |- valign=top | ||
+ | | '''presented at''': | ||
+ | | [http://www.isvlsi.org/ IEEE Computer Society Annual Symposium on VLSI (ISVLSI)], Pittsburgh, USA, 2016. | ||
+ | |} | ||
+ | |||
+ | | align=center width="70" | | ||
+ | <span class="plainlinks"> | ||
+ | [[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/8/8f/Morgul_Peker_Altun_Power-Delay-Area_Performance_Modeling_and_Analysis_for_Nano-Crossbar_Arrays.pdf]]</span> | ||
+ | <br> | ||
+ | [[Media:Morgul_Peker_Altun_Power-Delay-Area_Performance_Modeling_and_Analysis_for_Nano-Crossbar_Arrays.pdf | Paper]] | ||
+ | | align="center" width="70" | | ||
+ | <span class="plainlinks"> | ||
+ | |||
+ | [[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/5/5a/Morgul_Peker_Altun_Power-Delay-Area_Performance_Modeling_and_Analysis_for_Nano-Crossbar_Arrays.pptx]] | ||
+ | </span> | ||
+ | <br> [http://www.ecc.itu.edu.tr/images/5/5a/Morgul_Peker_Altun_Power-Delay-Area_Performance_Modeling_and_Analysis_for_Nano-Crossbar_Arrays.pptx Poster] | ||
+ | |} | ||
+ | |||
+ | === Fault/Defect/Variation Tolerance === | ||
+ | |||
+ | {| style="border:2px solid #abd5f5; background:#f1f5fc;" | ||
+ | | | ||
+ | {| | ||
+ | |- valign=top | ||
+ | | width="100" |'''title''': | ||
+ | | width="624"|[[Media:Tunali_Morgul_Altun_Defect_Tolerant_Memristor_Crossbars.pdf | Defect Tolerant Logic Synthesis for Memristor Crossbars with Performance Evaluation]] | ||
+ | |- valign="top" | ||
+ | | '''authors''': | ||
+ | | Onur Tunali, Ceylan Morgul, and [[Mustafa Altun]] | ||
+ | |- valign="top" | ||
+ | | '''appeared in''': | ||
+ | | width="624" | [http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=40 IEEE Micro], Vol. 38, Issue 5, pp. 22–31, 2018. | ||
+ | |} | ||
+ | | align=center width="70" | | ||
+ | <span class="plainlinks"> | ||
+ | [[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/d/db/Tunali_Morgul_Altun_Defect_Tolerant_Memristor_Crossbars.pdf]]</span> | ||
+ | <br> | ||
+ | [[Media:Tunali_Morgul_Altun_Defect_Tolerant_Memristor_Crossbars.pdf | Paper]] | ||
+ | |} | ||
+ | |||
+ | {| style="border:2px solid #abd5f5; background:#f1f5fc;" | ||
+ | | | ||
+ | {| | ||
+ | |- valign=top | ||
+ | | width="100" |'''title''': | ||
+ | | width="624"|[[Media:Peker_Altun_Variation_Tolerant_Logic_Mapping_of_Nano_Crossbars.pdf | A Fast Hill Climbing Algorithm for Defect and Variation Tolerant Logic Mapping of Nano-Crossbar Arrays]] | ||
+ | |- valign="top" | ||
+ | | '''authors''': | ||
+ | | Furkan Peker and [[Mustafa Altun]] | ||
+ | |- valign="top" | ||
+ | | '''appeared in''': | ||
+ | | width="624" | [http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=6687315 IEEE Transactions on Multi-Scale Computing Systems], Vol. 4, No. 4, pp. 522–532, 2018. | ||
+ | |} | ||
+ | | align=center width="70" | | ||
+ | <span class="plainlinks"> | ||
+ | [[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/7/71/Peker_Altun_Variation_Tolerant_Logic_Mapping_of_Nano_Crossbars.pdf]]</span> | ||
+ | <br> | ||
+ | [[Media:Peker_Altun_Variation_Tolerant_Logic_Mapping_of_Nano_Crossbars.pdf | Paper]] | ||
|} | |} | ||
Line 87: | Line 245: | ||
| Onur Tunali and [[Mustafa Altun]] | | Onur Tunali and [[Mustafa Altun]] | ||
|- valign="top" | |- valign="top" | ||
− | | ''' | + | | '''presented at''': |
| width="550"| [http://icecs2017.org/ IEEE International Conference on Electronics Circuits and Systems (ICECS)], Batumi, Georgia, 2017. | | width="550"| [http://icecs2017.org/ IEEE International Conference on Electronics Circuits and Systems (ICECS)], Batumi, Georgia, 2017. | ||
|} | |} | ||
Line 133: | Line 291: | ||
| Onur Tunali and [[Mustafa Altun]] | | Onur Tunali and [[Mustafa Altun]] | ||
|- valign="top" | |- valign="top" | ||
− | | ''' | + | | '''appeared in''': |
| width="624" | [http://csur.acm.org/ ACM Computing Surveys], Vol. 50, No. 6, Article 79, 2017. | | width="624" | [http://csur.acm.org/ ACM Computing Surveys], Vol. 50, No. 6, Article 79, 2017. | ||
|} | |} | ||
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{| style="border:2px solid #abd5f5; background:#f1f5fc;" | {| style="border:2px solid #abd5f5; background:#f1f5fc;" | ||
− | |||
| | | | ||
{| | {| | ||
|- valign=top | |- valign=top | ||
| width="100" |'''title''': | | width="100" |'''title''': | ||
− | | width=" | + | | width="624"|[[Media:Tunali_Altun_Permanent_and_Transient_Fault_Tolerance_for_Reconfigurable_Nano-Crossbar_Arrays.pdf | Permanent and Transient Fault Tolerance for Reconfigurable Nano-Crossbar Arrays]] |
|- valign="top" | |- valign="top" | ||
| '''authors''': | | '''authors''': | ||
− | | | + | | Onur Tunali and [[Mustafa Altun]] |
− | |- valign=top | + | |- valign="top" |
| '''appeared in''': | | '''appeared in''': | ||
− | | width="624" | [http:// | + | | width="624" | [http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=43 IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems], Vol. 36, Issue 5, pp. 747–760, 2017. |
|} | |} | ||
| align=center width="70" | | | align=center width="70" | | ||
<span class="plainlinks"> | <span class="plainlinks"> | ||
− | [[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/ | + | [[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/c/cc/Tunali_Altun_Permanent_and_Transient_Fault_Tolerance_for_Reconfigurable_Nano-Crossbar_Arrays.pdf]]</span> |
<br> | <br> | ||
− | [[Media: | + | [[Media:Tunali_Altun_Permanent_and_Transient_Fault_Tolerance_for_Reconfigurable_Nano-Crossbar_Arrays.pdf | Paper]] |
− | + | ||
|} | |} | ||
Line 170: | Line 326: | ||
|- valign=top | |- valign=top | ||
| width="100" |'''title''': | | width="100" |'''title''': | ||
− | | width="550"|[[Media: | + | | width="550"|[[Media:Tunali_Altun_Defect_Tolerance_in_Diode_FET_and_Four-Terminal_Switch_based_Nano-Crossbar_Arrays.pdf | Defect Tolerance in Diode FET and Four-Terminal Switch Based Nano-Crossbar Arrays]] |
|- valign="top" | |- valign="top" | ||
| '''authors''': | | '''authors''': | ||
− | | [[Mustafa Altun]] | + | | Onur Tunali and [[Mustafa Altun]] |
|- valign="top" | |- valign="top" | ||
| '''presented at''': | | '''presented at''': | ||
− | | [http://www. | + | | width="550"|[http://www.nanoarch.org/ IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH)], Boston, USA, 2015. |
|} | |} | ||
| align=center width="70" | | | align=center width="70" | | ||
<span class="plainlinks"> | <span class="plainlinks"> | ||
− | [[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/ | + | [[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/e/ee/Tunali_Altun_Defect_Tolerance_in_Diode_FET_and_Four-Terminal_Switch_based_Nano-Crossbar_Arrays.pdf]]</span> |
<br> | <br> | ||
− | [[Media: | + | [[Media:Tunali_Altun_Defect_Tolerance_in_Diode_FET_and_Four-Terminal_Switch_based_Nano-Crossbar_Arrays.pdf | Paper]] |
| align="center" width="70" | | | align="center" width="70" | | ||
<span class="plainlinks"> | <span class="plainlinks"> | ||
− | [[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/ | + | [[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/f/f9/Tunali_Altun_Defect_Tolerance_in_Diode_FET_and_Four-Terminal_Switch_based_Nano-Crossbar_Arrays.pptx]] |
</span> | </span> | ||
− | <br> [http://www.ecc.itu.edu.tr/images/ | + | <br> [http://www.ecc.itu.edu.tr/images/f/f9/Tunali_Altun_Defect_Tolerance_in_Diode_FET_and_Four-Terminal_Switch_based_Nano-Crossbar_Arrays.pptx Slides] |
|} | |} | ||
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|- valign=top | |- valign=top | ||
| width="100" |'''title''': | | width="100" |'''title''': | ||
− | | width="624"|[[Media: | + | | width="624"|[[Media:Altun_Riedel_Synthesizing_Logic_with_Percolation_in_Nanoscale_Lattices.pdf | Synthesizing Logic with Percolation in Nanoscale Lattices]] |
|- valign="top" | |- valign="top" | ||
| '''authors''': | | '''authors''': | ||
− | | | + | | [[Mustafa Altun]] and Marc Riedel |
|- valign="top" | |- valign="top" | ||
| '''appeared in''': | | '''appeared in''': | ||
− | + | | [http://www.igi-global.com/Bookstore/TitleDetails.aspx?TitleId=1117&DetailsType=Description/ International Journal of Nanotechnology and Molecular Computation], Vol. 3, Issue 2, pp. 12–30, 2011. | |
|} | |} | ||
+ | |||
| align=center width="70" | | | align=center width="70" | | ||
<span class="plainlinks"> | <span class="plainlinks"> | ||
− | [[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/ | + | [[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/3/3b/Altun_Riedel_Synthesizing_Logic_with_Percolation_in_Nanoscale_Lattices.pdf]]</span> |
<br> | <br> | ||
− | [[Media: | + | [[Media:Altun_Riedel_Synthesizing_Logic_with_Percolation_in_Nanoscale_Lattices.pdf | Paper]] |
|} | |} | ||
Line 217: | Line 374: | ||
|- valign=top | |- valign=top | ||
| width="100" |'''title''': | | width="100" |'''title''': | ||
− | | width="550"|[[Media: | + | | width="550"|[[Media:Altun_Riedel_Neuhauser_Nanoscale_Digital_Computation_Through_Percolation.pdf | Nanoscale Digital Computation Through Percolation]] |
|- valign="top" | |- valign="top" | ||
| '''authors''': | | '''authors''': | ||
− | | | + | | [[Mustafa Altun]], Marc Riedel, and [http://www.cbs.umn.edu/eeb/contacts/claudia-neuhauser/ Claudia Neuhauser] |
|- valign=top | |- valign=top | ||
| '''presented at''': | | '''presented at''': | ||
− | | [http:// | + | | [http://www.dac.com IEEE/ACM Design Automation Conference (DAC)], San Francisco, USA, 2009. |
|} | |} | ||
| align=center width="70" | | | align=center width="70" | | ||
<span class="plainlinks"> | <span class="plainlinks"> | ||
− | [[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/ | + | [[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/0/0c/Altun_Riedel_Neuhauser_Nanoscale_Digital_Computation_Through_Percolation.pdf]]</span> |
<br> | <br> | ||
− | [[Media: | + | [[Media:Altun_Riedel_Neuhauser_Nanoscale_Digital_Computation_Through_Percolation.pdf | Paper]] |
| align="center" width="70" | | | align="center" width="70" | | ||
<span class="plainlinks"> | <span class="plainlinks"> | ||
− | [[File: | + | [[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/f/fe/Altun_Riedel_Neuhauser_Nanoscale_Digital_Computation_Through_Percolation.ppt]] |
</span> | </span> | ||
− | <br> [ | + | <br> [http://www.ecc.itu.edu.tr/images/f/fe/Altun_Riedel_Neuhauser_Nanoscale_Digital_Computation_Through_Percolation.ppt Slides] |
|} | |} | ||
+ | |||
+ | === Logic Synthesis === | ||
{| style="border:2px solid #abd5f5; background:#f1f5fc;" | {| style="border:2px solid #abd5f5; background:#f1f5fc;" | ||
| | | | ||
− | {| | + | {| |
|- valign=top | |- valign=top | ||
| width="100" |'''title''': | | width="100" |'''title''': | ||
− | | width="550"|[[Media: | + | | width="550"|[[Media: Aksoy_Altun_SAT_based_Synthesis_of_Switching_Lattices.pdf| A Satisfiability-Based Approximate Algorithm for Logic Synthesis Using Switching Lattices]] |
|- valign="top" | |- valign="top" | ||
| '''authors''': | | '''authors''': | ||
− | | | + | | Levent Aksoy and [[Mustafa Altun]] |
− | |- valign=top | + | |- valign="top" |
| '''presented at''': | | '''presented at''': | ||
− | | [http://www. | + | | width="550"| [http://www.date-conference.com/ Design, Automation and Test in Europe (DATE)], Florence, Italy, 2019. |
|} | |} | ||
− | + | | align=center width="70" | | |
− | | align=center width="70" | | + | |
<span class="plainlinks"> | <span class="plainlinks"> | ||
− | [[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/ | + | [[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/f/fe/Aksoy_Altun_SAT_based_Synthesis_of_Switching_Lattices.pdf]]</span> |
<br> | <br> | ||
− | [[Media: | + | [[Media:Aksoy_Altun_SAT_based_Synthesis_of_Switching_Lattices.pdf | Paper]] |
− | | align="center" width="70" | | + | | align="center" width="70" | |
<span class="plainlinks"> | <span class="plainlinks"> | ||
− | [[File:PPT.jpg|60px|link= | + | [[File:PPT.jpg|60px|link=]] |
</span> | </span> | ||
− | <br> | + | <br> |
+ | Slides | ||
|} | |} | ||
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|- valign=top | |- valign=top | ||
| width="100" |'''title''': | | width="100" |'''title''': | ||
− | | width=" | + | | width="624"|[[Media:Morgul_Altun_Algorithms_for_Switching_Lattices.pdf | Optimal and Heuristic Algorithms to Synthesize Lattices of Four-Terminal Switches]] |
|- valign="top" | |- valign="top" | ||
| '''authors''': | | '''authors''': | ||
− | | | + | | Ceylan Morgul and [[Mustafa Altun]] |
|- valign="top" | |- valign="top" | ||
− | | ''' | + | | '''appeared in''': |
− | | width=" | + | | width="624" | [http://www.journals.elsevier.com/integration Integration, the VLSI Journal], Vol. 64, pp. 60–70, 2019. |
|} | |} | ||
| align=center width="70" | | | align=center width="70" | | ||
<span class="plainlinks"> | <span class="plainlinks"> | ||
− | [[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/ | + | [[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/5/58/Morgul_Altun_Algorithms_for_Switching_Lattices.pdf]]</span> |
<br> | <br> | ||
− | [[Media: | + | [[Media:Morgul_Altun_Algorithms_for_Switching_Lattices.pdf | Paper]] |
− | + | ||
− | + | ||
− | + | ||
− | + | ||
− | + | ||
− | + | ||
|} | |} | ||
Line 342: | Line 495: | ||
<br> | <br> | ||
[[Media:Altun_Riedel_Logic_Synthesis_for_Switching_Lattices.pdf | Paper]] | [[Media:Altun_Riedel_Logic_Synthesis_for_Switching_Lattices.pdf | Paper]] | ||
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|} | |} | ||
Line 389: | Line 521: | ||
</span> | </span> | ||
<br> [http://www.ecc.itu.edu.tr/images/2/28/Altun_Riedel_Lattice-Based_Computation_of_Boolean_Functions.ppt Slides] | <br> [http://www.ecc.itu.edu.tr/images/2/28/Altun_Riedel_Lattice-Based_Computation_of_Boolean_Functions.ppt Slides] | ||
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|} | |} | ||
Line 455: | Line 559: | ||
== Reversible Circuit Design == | == Reversible Circuit Design == | ||
+ | |||
+ | {| style="border:2px solid #abd5f5; background:#f1f5fc; " | ||
+ | |||
+ | | | ||
+ | {| | ||
+ | |- valign=top | ||
+ | | width="100" |'''title''': | ||
+ | | width="624"|[[Media:Altun_Parvin_Cilasun_Exploiting_Reversible_Computing_for_CMOS_Fault_Tolerance.pdf| Exploiting Reversible Computing for Latent-Fault-Free Error Detecting/Correcting CMOS Circuits | ||
+ | ]] | ||
+ | |- valign="top" | ||
+ | | '''authors''': | ||
+ | | [[Mustafa Altun]], Sajjad Parvin, and Husrev Cilasun | ||
+ | |- valign="top" | ||
+ | | '''appeared in''': | ||
+ | | [http://ieeeaccess.ieee.org/ IEEE Access], Vol. 6, pp. 74475–74484, 2018. | ||
+ | |} | ||
+ | | align=center width="70" | | ||
+ | <span class="plainlinks"> | ||
+ | [[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/7/7d/Altun_Parvin_Cilasun_Exploiting_Reversible_Computing_for_CMOS_Fault_Tolerance.pdf]]</span> | ||
+ | <br> | ||
+ | [[Media:Altun_Parvin_Cilasun_Exploiting_Reversible_Computing_for_CMOS_Fault_Tolerance.pdf | Paper]] | ||
+ | |||
+ | |} | ||
{| style="border:2px solid #abd5f5; background:#f1f5fc; " | {| style="border:2px solid #abd5f5; background:#f1f5fc; " | ||
Line 469: | Line 596: | ||
|- valign="top" | |- valign="top" | ||
| '''appeared in''': | | '''appeared in''': | ||
− | | [http://www.journals.istanbul.edu.tr/iujeee/index Istanbul University - Journal of Electrical & Electronics Engineering], Vol. 17, No. 1, pp. 3147 | + | | [http://www.journals.istanbul.edu.tr/iujeee/index Istanbul University - Journal of Electrical & Electronics Engineering], Vol. 17, No. 1, pp. 3147–3154, 2017. |
|} | |} | ||
| align=center width="70" | | | align=center width="70" | | ||
Line 491: | Line 618: | ||
|- valign="top" | |- valign="top" | ||
| '''appeared in''': | | '''appeared in''': | ||
− | | [http://www.oldcitypublishing.com/journals/mvlsc-home/ Journal of Multiple-Valued Logic and Soft Computing], Vol. 29, Issue 1-2, pp. | + | | [http://www.oldcitypublishing.com/journals/mvlsc-home/ Journal of Multiple-Valued Logic and Soft Computing], Vol. 29, Issue 1-2, pp. 1–23, 2017. |
|} | |} | ||
| align=center width="70" | | | align=center width="70" | | ||
Line 572: | Line 699: | ||
| Ensar Vahapoglu and [[Mustafa Altun]] | | Ensar Vahapoglu and [[Mustafa Altun]] | ||
|- valign="top" | |- valign="top" | ||
− | | ''' | + | | '''appeared in''': |
− | | width="624" | | + | | width="624" | arXiv, 1805.06262, 2018. |
|} | |} | ||
| align=center width="70" | | | align=center width="70" | | ||
Line 593: | Line 720: | ||
| Burak Karadeniz and [[Mustafa Altun]] | | Burak Karadeniz and [[Mustafa Altun]] | ||
|- valign="top" | |- valign="top" | ||
− | | ''' | + | | '''presented at''': |
| width="550"| [http://icecs2017.org/ IEEE International Conference on Electronics Circuits and Systems (ICECS)], Batumi, Georgia, 2017. | | width="550"| [http://icecs2017.org/ IEEE International Conference on Electronics Circuits and Systems (ICECS)], Batumi, Georgia, 2017. | ||
|} | |} | ||
Line 673: | Line 800: | ||
== Approximate Computing == | == Approximate Computing == | ||
+ | |||
+ | {| style="border:2px solid #abd5f5; background:#f1f5fc; " | ||
+ | |||
+ | | | ||
+ | {| | ||
+ | |- valign=top | ||
+ | | width="100" |'''title''': | ||
+ | | width="624"|[[Media:Ayhan_Altun_Circuit_Aware_Approximate_System_Design.pdf| Circuit Aware Approximate System Design with Case Studies in Image Processing and Neural Networks]] | ||
+ | |- valign="top" | ||
+ | | '''authors''': | ||
+ | | Tuba Ayhan and [[Mustafa Altun]] | ||
+ | |- valign="top" | ||
+ | | '''appeared in''': | ||
+ | | [http://ieeeaccess.ieee.org/ IEEE Access], Vol. 7, pp. 4726–4734, 2019. | ||
+ | |} | ||
+ | | align=center width="70" | | ||
+ | <span class="plainlinks"> | ||
+ | [[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/9/90/Ayhan_Altun_Circuit_Aware_Approximate_System_Design.pdf]]</span> | ||
+ | <br> | ||
+ | [[Media:Ayhan_Altun_Circuit_Aware_Approximate_System_Design.pdf | Paper]] | ||
+ | |||
+ | |} | ||
{| style="border:2px solid #abd5f5; background:#f1f5fc;" | {| style="border:2px solid #abd5f5; background:#f1f5fc;" | ||
Line 697: | Line 846: | ||
<span class="plainlinks"> | <span class="plainlinks"> | ||
− | [[File:PPT.jpg|60px|link=]] | + | [[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/a/a4/Ayhan_Altun_Approximate_Neural_Network_Generation.pptx]] |
</span> | </span> | ||
− | <br> Slides | + | <br> [http://www.ecc.itu.edu.tr/images/a/a4/Ayhan_Altun_Approximate_Neural_Network_Generation.pptx Slides] |
|} | |} | ||
Line 746: | Line 895: | ||
|- valign="top" | |- valign="top" | ||
| '''presented at''': | | '''presented at''': | ||
− | | width="550"| [http:// | + | | width="550"| [http://ieeexplore.ieee.org/xpl/conhome.jsp?punumber=1001786 Sinyal İşleme ve İletişim Uygulamaları Kurultayı (SİU)], Izmir, Turkey, 2018. |
|} | |} | ||
Line 764: | Line 913: | ||
|} | |} | ||
− | == | + | == Large-Area Electronics == |
− | === Transistor Modeling === | + | === Organic Transistor Modeling === |
{| style="border:2px solid #abd5f5; background:#f1f5fc;" | {| style="border:2px solid #abd5f5; background:#f1f5fc;" | ||
Line 791: | Line 940: | ||
<span class="plainlinks"> | <span class="plainlinks"> | ||
− | [[File:PPT.jpg|60px|link=]] | + | [[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/b/b9/Akkan_Altun_Sedef_OFET_Parameter_Extraction_with_ABC.pptx]] |
</span> | </span> | ||
− | <br> Slides | + | <br> [http://www.ecc.itu.edu.tr/images/b/b9/Akkan_Altun_Sedef_OFET_Parameter_Extraction_with_ABC.pptx Slides] |
|} | |} | ||
Line 810: | Line 959: | ||
|- valign="top" | |- valign="top" | ||
| '''appeared in''': | | '''appeared in''': | ||
− | | [http://journals.tubitak.gov.tr/elektrik/index.htm;jsessionid=848207EBE52EFE10C78B78C76A0FEAD9 Turkish Journal of Electrical Engineering and Computer Sciences], Vol. 25, No. 4, pp. | + | | [http://journals.tubitak.gov.tr/elektrik/index.htm;jsessionid=848207EBE52EFE10C78B78C76A0FEAD9 Turkish Journal of Electrical Engineering and Computer Sciences], Vol. 25, No. 4, pp. 3240–3252, 2017. |
|} | |} | ||
| align=center width="70" | | | align=center width="70" | | ||
Line 832: | Line 981: | ||
|- valign="top" | |- valign="top" | ||
| '''appeared in''': | | '''appeared in''': | ||
− | | [http://www.journals.elsevier.com/reliability-engineering-and-system-safety Reliability Engineering and System Safety], Vol. 156, pp. | + | | [http://www.journals.elsevier.com/reliability-engineering-and-system-safety Reliability Engineering and System Safety], Vol. 156, pp. 175–184, 2016. |
|} | |} | ||
| align=center width="70" | | | align=center width="70" | | ||
Line 949: | Line 1,098: | ||
</span> | </span> | ||
<br> [http://www.ecc.itu.edu.tr/images/e/eb/Comert_Yadavari_Altun_Erturk_Reliability_Prediction_of_Electronic_Boards_by_Analyzing_Field_Return_Data.pptx Slides] | <br> [http://www.ecc.itu.edu.tr/images/e/eb/Comert_Yadavari_Altun_Erturk_Reliability_Prediction_of_Electronic_Boards_by_Analyzing_Field_Return_Data.pptx Slides] | ||
+ | |} | ||
+ | |||
+ | ==== National Publications in Turkish ==== | ||
+ | |||
+ | {| style="border:2px solid #abd5f5; background:#f1f5fc;" | ||
+ | |||
+ | | | ||
+ | {| | ||
+ | |- valign=top | ||
+ | | width="100" |'''title''': | ||
+ | | width="550"|[[Media:Avci_Altun_Reliability Model_for_MOSFET_GOB.pdf | A New Reliability Model for MOSFET Gate Oxide Breakdown]] | ||
+ | |- valign="top | ||
+ | | width="100" |'''title (in Turkish)''': | ||
+ | | width="550"|[[Media:Avci_Altun_Reliability_Model_for_MOSFET_GOB.pdf | MOSFET Geçit Oksidi Kırılması için Yeni Bir Güvenilirlik Modeli]] | ||
+ | |- valign="top | ||
+ | | '''authors''': | ||
+ | | Hasan Avci and [[Mustafa Altun]] | ||
+ | |- valign="top" | ||
+ | | '''presented at''': | ||
+ | | width="550"| [http://www.eleco.org.tr/ Elektrik, Elektronik, Bilgisayar ve Biyomedikal Mühendisliği Sempozyumu (ELECO)], Bursa, Turkey, 2018. | ||
+ | |} | ||
+ | |||
+ | | align=center width="70" | | ||
+ | <span class="plainlinks"> | ||
+ | |||
+ | [[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/6/6f/Avci_Altun_Reliability_Model_for_MOSFET_GOB.pdf]]</span> | ||
+ | <br> | ||
+ | [[Media:Avci_Altun_Reliability_Model_for_MOSFET_GOB.pdf | Paper]] | ||
+ | |||
+ | | align="center" width="70" | | ||
+ | <span class="plainlinks"> | ||
+ | |||
+ | [[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/f/f9/Avci_Altun_Reliability_Model_for_MOSFET_GOB.pptx]] | ||
+ | </span> | ||
+ | <br> [http://www.ecc.itu.edu.tr/images/f/f9/Avci_Altun_Reliability_Model_for_MOSFET_GOB.pptx Slides] | ||
|} | |} | ||
Line 1,264: | Line 1,448: | ||
|- valign="top" | |- valign="top" | ||
| '''appeared in''': | | '''appeared in''': | ||
− | | [http://www.springer.com/mathematics/applications/journal/10255 Acta Mathematicae Applicatae Sinica - English Series], Vol. 33, Issue 1, pp. 43 | + | | [http://www.springer.com/mathematics/applications/journal/10255 Acta Mathematicae Applicatae Sinica - English Series], Vol. 33, Issue 1, pp. 43–52, 2017. |
|} | |} | ||
Revision as of 23:48, 31 January 2019
Listed below are the papers, first authored by our group members as an indication that the related research is mainly conducted in our group, and the presentations. Research topics are ordered from newest to oldest as well as by considering their importance. Under each topic, papers are ordered from newest to oldest. All materials are subject to copyrights.
Contents |
Computing with Nano-Crossbar Arrays
Technology Development
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Comprehensive Performance Optimization
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Fault/Defect/Variation Tolerance
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Logic Synthesis
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National Publications in Turkish
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Reversible Circuit Design
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National Publications in Turkish
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Stochastic and Bit Stream Computing
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National Publications in Turkish
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Approximate Computing
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National Publications in Turkish
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Large-Area Electronics
Organic Transistor Modeling
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Reliability of Electronic Products
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National Publications in Turkish
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Analog Circuit Design
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National Publications in Turkish
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Discrete Mathematics
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