EHB 205E
From The Emerging Circuits and Computation Group at ITU
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== Announcements == | == Announcements == | ||
| − | + | * <span style="background:#4682B4; color:#FFFFFF; font-size: 100%;"> Sept. 14th</span> The class is given in the room '''4102''' (first floor), EEF. | |
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| − | * <span style="background:#4682B4; color:#FFFFFF; font-size: 100%;"> Sept. | + | |
== Syllabus == | == Syllabus == | ||
| − | <div style="font-size: 120%;"> '''EHB 205E: Introduction to Logic Design''', CRN: | + | <div style="font-size: 120%;"> '''EHB 205E: Introduction to Logic Design''', CRN: 11101, Tuesdays 12:30-15:30, Room: 5202 (EEF), Fall 2019. </div> |
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| <div style="font-size: 120%;"> '''Teaching Assistant'''</div> | | <div style="font-size: 120%;"> '''Teaching Assistant'''</div> | ||
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| − | + | Emre Altuner | |
| − | * Email: | + | * Email: altuner16@itu.edu.tr |
| − | * Room: | + | * Room: 3107 EEF |
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| <div style="font-size: 120%;"> '''Grading'''</div> | | <div style="font-size: 120%;"> '''Grading'''</div> | ||
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* Homeworks are due at the beginning of class. Late homeworks will be downgraded by '''20%''' for each day passed the due date. | * Homeworks are due at the beginning of class. Late homeworks will be downgraded by '''20%''' for each day passed the due date. | ||
* Exams are in '''closed-notes''' and '''closed-books''' format. | * Exams are in '''closed-notes''' and '''closed-books''' format. | ||
| − | * To be eligible of taking the final | + | * To be eligible of taking the final exam, you should take both midterms and your midterm average should be at least '''25''' (out of 100). |
| + | * To pass the course, you should have total of at least '''30''' (out of 100). | ||
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Revision as of 10:38, 14 September 2019
Contents |
Announcements
- Sept. 14th The class is given in the room 4102 (first floor), EEF.
Syllabus
EHB 205E: Introduction to Logic Design, CRN: 11101, Tuesdays 12:30-15:30, Room: 5202 (EEF), Fall 2019.
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Instructor
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| Teaching Assistant
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Emre Altuner
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| Grading
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| Textbook
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| Reference Books
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| Policies
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Weekly Course Plan
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Date
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Topic
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| Week 1, 18/9/2018 | Introduction |
| Week 2, 25/9/2018 | Digital logic fundamentals: gates, combinational circuits, Boolean expressions |
| Week 3, 2/10/2018 | Digital logic fundamentals: truth tables, two-level forms (AND/OR/NAND/NOR), "don't cares" |
| Weeks 4, 9/10/2018 | Logic minimization: Karnaugh maps, Quine-McCluskey method |
| Weeks 5, 16/10/2018 | Quine-McCluskey method, binary decision diagrams, hazards |
| Week 6, 23/10/2018 | Combinational circuit design: building blocks (adders, multiplexers, decoders, etc.) |
| Weeks 7, 30/10/2018 | MIDTERM I |
| Week 8, 6/11/2018 | HOLIDAY, no class |
| Week 9, 13/11/2018 | Combinational circuit design: implementing Boolean and arithmetic operations |
| Weeks 10, 20/11/2018 | Area-Delay Performance analysis of combinational circuits |
| Week 11, 27/11/2018 | Sequential circuits: latches & flip-flops |
| Week 12, 4/12/2018 | MIDTERM II |
| Weeks 13, 11/12/2018 | Sequential circuit design: state graphs and tables, modules |
| Weeks 14, 18/12/2018 | Sequential circuit design: modules, state machines |
| Weeks 15, 25/12/2018 | Sequential circuit design: modules, state machines |
Course Materials
| Homeworks & Solutions | Homeworks & Solutions | Quizzes & Solutions | Sample Problems & Solutions | Exams |
|---|---|---|---|---|
| Homework 1 & Solutions | Homework 3 | Quiz 1 & Solutions | Problem Set 1 & Solutions | Midterm 1 |
| Homework 2 & Solutions | Homework 4 | Quiz 2 & Solutions | Problem Set 2 & Solutions | Midterm 2 |
